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| qe1f- plus device quad e1 framer- plus TXC-03114 document number: preliminary TXC-03114-mb ed. 2, july 1999 ? offline framer supports standard and frame hold- off frame alignment with crc-4 multiframe check and selectable out of frame criteria, and transparent non-framing mode frame alignment detection and loss of frame alignment declaration comply with itu-t g.706 dual unipolar (hdb3/ami) or nrz line interface two-frame slip buffers in both receive and transmit directions supports channel associated signaling in time slot 16 detects and forces rai and ais alarms; detects oof and cfa framing conditions hdlc processing using national bits in time slot 0 (up to 20 kbit/s) detects, counts and forces line code errors (bpvs), crc-4 errors, and frame bit errors system interfaces - 2 mbit/s, 8 mbit/s and 16 mbit/s transmission modes with gapped clock option for 2 mbit/s - 2 mbit/s mvip ? mode, 8 mbit/s h-mvip ? /h.100 mode and 16 mbit/s pcm highway mode with gapped clock option for 2 mbit/s mvip motorola/intel-compatible microprocessor interface one-second interrupt input latches counter values and line events into shadow registers local and remote line loopbacks boundary scan capability (ieee 1149.1) single +3.3 or +5 volt, 5% power supply 128-pin low profile plastic quad flat package the qe1f- plus is a four-channel e1 (2048 kbit/s) framer designed for voice and data communications applications. a dual unipolar or nrz line interface is supported with full alarm detection and generation per itu-t g.703. the transmit and receive sections of each of the four framers are independent, with individual two-frame slip buffers, which allows operation with a wide range of switching and transmission products. framing algorithm support for itu-t g.704, g.706 and ets 300 011. access and control for signaling and data are provided via a motorola/intel- compatible microprocessor interface. for hdlc link applications, each framer supplies a full duplex hdlc controller in addition to on-board latching of all required performance parameters; minimal software overhead is required. diagnostic, test, and maintenance functions are provided, including e1 local and remote loopbacks, time slot loopbacks and boundary scan (ieee 1149.1). sdh terminal or add/drop multiplexers supporting e1 byte synchronous operation dcs, digital central office or remote digital terminals e1 multiplexers e1 and fractional e1 csus atm products with integrated e1 interfaces lan routers with integrated e1 interfaces multichannel e1 test equipment qe1f- plus TXC-03114 nrz data and signaling highways quad e1 framer- plus e1 dual unipolar (rail)/nrz data & clocks transceiver serial interface microprocessor interface system & fallback clocks ieee 1149.1 ( jtag ) interface system (terminal) side line side interrupt/select 4 x 3 4 x 3 4 x 2 4 x 4 4 x 4 system i/o clocks copyright ? 1999 transwitch corporation transwitch and txc are registered trademarks of transwitch corporation mvip is a registered trademark of go-mvip, inc. data sheet preliminary information documents contain information on products in the sampling, pre-production or early production phases of the product life cycle. characteristic data and other specifications are subject to change. contact transwitch applications engineering for current information on this product. applications description features transwitch corporation ? 3 enterprise drive shelton, connecticut 06484 usa tel: 203-929-8810 fax: 203-926-9453 www.transwitch.com
-2 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet table of contents section page list of figures ............................................................................................................. 3 quad e1 framer- plus features................................................................................................. 5 block diagram ................................................................................................................. .......... 9 block diagram description...................................................................................................... . 10 pin diagram .................................................................................................................... ......... 14 pin descriptions ............................................................................................................... ........ 15 absolute maximum ratings and environmental limitations ................................................... 25 thermal characteristics ........................................................................................................ ... 25 power requirements for v dd = 5 volt ...................................................................................... 25 power requirements for v dd = 3.3 volt ................................................................................... 25 input, output and i/o parameters............................................................................................ 26 input/output parameters for 5 volt operation................................................................... 28 input/output parameters for 3.3 volt operation................................................................ 31 timing characteristics ......................................................................................................... .... 32 operation ...................................................................................................................... ........... 65 line interface selection .................................................................................................... 65 line interface control ....................................................................................................... 6 7 monitor mode................................................................................................................... . 67 system interface............................................................................................................... 68 2 mbit/s transmission mode............................................................................................. 71 8 mbit/s transmission mode............................................................................................. 75 16 mbit/s transmission mode........................................................................................... 77 2 mbit/s mvip mode ......................................................................................................... 78 8 mbit/s h-mvip/h.100 mode ........................................................................................... 81 16 mbit/s pcm highway mode ......................................................................................... 83 transmit and receive synchronization ............................................................................ 85 fractional e1 capability.................................................................................................... 86 framing........................................................................................................................ ..... 86 throughput delay ............................................................................................................. 9 6 signaling ...................................................................................................................... ..... 96 clocking and synchronization ........................................................................................ 100 ais detection and generation ........................................................................................ 102 hdlc channel................................................................................................................ 10 3 alarms......................................................................................................................... .... 106 maintenance ................................................................................................................... 109 local loopback ....................................................................................................... 109 remote line loopback ............................................................................................ 110 payload remote loopback ..................................................................................... 110 time slot remote loopback ................................................................................... 111 boundary scan ............................................................................................................... 11 2 reset procedure............................................................................................................. 11 8 memory map ..................................................................................................................... ..... 119 common registers .......................................................................................................... 119 per channel control and status indication registers ..................................................... 121 memory map descriptions ..................................................................................................... 12 8 common registers ......................................................................................................... 128 -3 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet section page per channel control and status indication registers .................................................... 138 application diagram............................................................................................................ ... 180 package information ............................................................................................................ .. 181 ordering information ........................................................................................................... ... 182 related products ............................................................................................................... .... 182 standards documentation sources ....................................................................................... 184 list of data sheet changes ................................................................................................... 1 86 documentation update registration form* ...................................................................... 191 * please note that transwitch provides documentation for all of its products. customers who are using a transwitch product, or planning to do so, should register with the transwitch marketing department to receive relevant updated and supplemental documentation as it is issued. they should also contact the applications engineering department to ensure that they are provided with the latest available information about the product, especially before undertaking development of new designs incorporating the product. list of figures figure page 1. qe1f- plus TXC-03114 block diagram ...................................................................................... 9 2. qe1f- plus TXC-03114 pin diagram........................................................................................ 14 3. dual unipolar (rail) receive interface timing ......................................................................... 32 4. dual unipolar (rail) transmit interface timing ........................................................................ 33 5. nrz receive interface timing (external transceiver)............................................................. 34 6. nrz transmit interface timing (external transceiver)............................................................ 35 7. nrz receive interface timing (fast sync mode).................................................................... 36 8. nrz transmit interface timing (fast sync mode)................................................................... 37 9. serial port write timing .................................................................................................... ....... 38 10. serial port read timing .................................................................................................... ....... 39 11. monitor mode timing........................................................................................................ ........ 40 12. receive highway timing - 2 mbit/s transmission mode (recovered receive line clock) ..... 41 13. receive highway timing - 2 mbit/s transmission mode (system clock) ............................... 42 14. receive highway timing - 8 mbit/s transmission mode.......................................................... 43 15. transmit highway timing - 8 mbit/s transmission mode......................................................... 44 16. receive highway timing - 16 mbit/s transmission mode........................................................ 45 17. transmit highway timing - 16 mbit/s transmission mode....................................................... 46 18. transmit highway timing - 2 mbit/s transmission mode......................................................... 47 19. receive highway timing - 2 mbit/s mvip mode ...................................................................... 48 20. transmit highway timing - 2 mbit/s mvip mode ..................................................................... 49 21. receive highway timing - 8 mbit/s h-mvip/ h.100 mode....................................................... 50 22. transmit highway timing - 8 mbit/s h-mvip/h.100 mode....................................................... 51 23. receive highway timing - 16 mbit/s pcm highway mode ...................................................... 52 24. transmit highway timing - 16 mbit/s pcm highway mode ..................................................... 53 25. receive highway timing - fractional e1 gapped clock (transmission mode; receive line clock)............................................................................... 54 26. receive highway timing - fractional e1 gapped clock (transmission and 2 mbit/s mvip modes; system clock) ....................................................... 55 -4 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet figure page 27. transmit highway timing - fractional e1 gapped clock (transmission and 2 mbit/s mvip modes) ............................................................................... 56 28. shadow register timing ..................................................................................................... ..... 57 29. boundary scan timing ....................................................................................................... ...... 58 30. intel microprocessor read cycle timing.................................................................................. 59 31. intel microprocessor write cycle timing.................................................................................. 6 0 32. motorola microprocessor read cycle timing .......................................................................... 62 33. motorola microprocessor write cycle timing........................................................................... 63 34. clock reference timing ..................................................................................................... ...... 64 35. line interface for dual unipolar mode...................................................................................... 65 36. line interface for nrz mode ................................................................................................ .... 66 37. transceiver serial i/o timing.............................................................................................. ..... 67 38. 8 mbit/s transmission mode and 8 mbit/s h-mvip/h.100 mode system interfaces................ 69 39. 16 mbit/s transmission mode and 16 mbit/s pcm highway mode system interfaces ............ 70 40. transmit highway - 2 mbit/s transmission mode .................................................................... 72 41. receive highway - 2 mbit/s transmission mode ..................................................................... 74 42. transmit highway - 8 mbit/s transmission mode .................................................................... 75 43. receive highway - 8 mbit/s transmission mode ..................................................................... 76 44. transmit highway - 16 mbit/s transmission mode .................................................................. 77 45. receive highway - 16 mbit/s transmission mode ................................................................... 78 46. transmit highway - 2 mbit/s mvip mode ................................................................................. 79 47. receive highway - 2 mbit/s mvip mode .................................................................................. 80 48. transmit highway - 8 mbit/s h-mvip/h.100 mode................................................................... 81 49. receive highway - 8 mbit/s h-mvip/h.100 mode.................................................................... 82 50. transmit highway - 16 mbit/s pcm highway mode ................................................................. 83 51. receive highway - 16 mbit/s pcm highway mode .................................................................. 84 52. transmit slip buffer....................................................................................................... ........... 94 53. receive slip buffer........................................................................................................ ........... 95 54. receive signaling buffer ................................................................................................... ....... 98 55. transmit signaling buffer .................................................................................................. ....... 99 56. hdlc format ................................................................................................................ ......... 103 57. shadow register operation .................................................................................................. . 108 58. local loopback ............................................................................................................. ......... 109 59. remote line loopback ....................................................................................................... ... 110 60. payload remote loopback .................................................................................................... 110 61. time slot remote loopback .................................................................................................. 111 62. boundary scan schematic .................................................................................................... . 113 63. some qe1f- plus TXC-03114 applications............................................................................ 180 64. qe1f- plus TXC-03114 128-pin low profile plastic quad flat package............................... 181 -5 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet quad e1 framer- plus features the quad e1 framer- plus (qe1f- plus ) device is a highly-featured four-channel e1 framer for use in a wide variety of interface, transmission and switching applications. four independent e1 framers are provided in a single monolithic vlsi device using sub-micron cmos technology. powered from a single +5.0 volt supply, the four framers dissipate less than one half of a watt typically. powered from a single +3.3 volt supply, the four framers dissipate less than one sixth of a watt typically. the qe1f- plus is provided in a rectangular 128-pin low profile quad flat package. its ambient operating temperature range extends from -40 o c to +85 o c. the qe1f- plus device has been designed to meet the latest industry standards, namely: itu-t g.703 physical/electrical characteristics of hierarchical digital interfaces itu-t g.704 synchronous frame structures used at primary and secondary hierarchical levels itu-t g.706 frame alignment and cyclic redundancy check (crc) procedures relating to basic frame structures defined in recommendation g.704 itu-t g.732 characteristics of primary pcm multiplex equipment operating at 2048 kbit/s itu-t g.735 characteristics of primary pcm multiplex equipment operating at 2048 kbit/s and offering synchronous digital access at 384 kbit/s and/or 64 kbit/s itu-t g.775 loss of signal (los) and alarm indication signal (ais) defect detection and clearance criteria itu-t g.821 error performance of an international digital connection forming part of an integrated services digital network itu-t g.823 the control of jitter and wander within digital networks which are based on the 2048 kbit/s hierarchy itu-t i.431 isdn user-network interfaces. primary rate user-network interface - layer 1 specification itu-t o.151 error performance measuring equipment operating at the primary rate and above itu-t q.516 operation and maintenance functions prets 300 011 integrated services digital network (isdn); primary rate user-network. nov. 1996 draft ieee 1149.1 standard test access port and boundary-scan architecture, may 1990 mvip, h-mvip multi-vendor integration protocol. working document, april 1995 enterprise computer telephony forum, h.100 rev. 1.0 hardware compatibility spec. ct bus the following features are available in the qe1f- plus device: framing modes: off line framer (data passes un-interrupted from line to system in or out of frame alignment) follows itu-t g.706 ( ? 88 or ? 91) frame alignment detection and loss of alignment declaration thirty-two 64 kbit/s time slots basic frame structure ts0/crc-4 multiframe - two fas selectable algorithms (standard and frame hold-off) - frame alignment and multiframe alignment per ets 300 011 - crc-4 and non crc-4 multiframing automatic interworking per itu-t g.706 (1991 annex b) ts16/signaling multiframe - two mas selectable algorithms (standard and enhanced) line codes: ami hdb3 nrz (unipolar) -6 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet signaling methods: common channel signaling (ccs) with inversion of transmit or receive and substitution of 0000 with 1111 to the transmit line channel associated signaling (cas) in time slot 16 signaling access: dedicated signaling bus data stream embedded internal registers (microprocessor interface) system interface: separate transmit and receive paths for all modes 2048 kbit/s separate data and signaling bus for each of the 4 framers - transmission mode with 500 hz multiframe signal each direction and 8 signaling bits per frame - mvip mode with 8 khz framing signal each direction and all signaling bits per frame 2048 kbit/s separate data bus for each of the 4 framers with continuous and gapped clock transmission mode with 500 hz multiframe signal and selectable per time slot clock each direction 8192 kbit/s separate data and signaling bus byte-interleaved by all 4 framers with 16384 kbit/s clock - transmission mode with 500 hz multiframe signal each direction and 8 signaling bits per frame - h-mvip/h.100 mode with 8 khz framing signal each direction and all signaling bits per frame 16384 kbit/s combined data and signaling bus bit-interleaved by all 4 framers with 16384 kbit/s clock - transmission mode with 500 hz multiframe signal each direction and 8 signaling bits per frame - pcm highway mode with 8 khz framing signal each direction and all signaling bits per frame dual reference clock outputs; any 2 e1s brought to bus pins for multiple qe1f- plus tri-statable output ports gapped clock option for fractional e1 support in transmission mode in place of signaling highways programmable sync start position microprocessor interface: intel compatible interface motorola compatible interface directly addressable control and status registers all interrupts are maskable external line interface unit port: serial port for the control of external line interface components programmable for unipolar or bipolar interface individual chip select and interrupt signals for each transceiver integration of line interface unit alarms -7 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet maintenance functions: loopbacks - local - line remote - payload remote - per time slot remote in transmission mode only pattern generation/detection per e1 - force programmable code in any time slot via slip buffer access - transmit and detect loop codes via read and write of the slip buffer ram - prbs generator/analyzer (2 15 - 1) with out of lock pin for board testing available in 2 mbit/s transmission mode - transmit ais - all 1's only in the information bits - idle code insertion error insertion - bpv - crc-4 - fas/nfas - los data link access - full-duplex hdlc message controller supporting back to back frames - 8-bit access via microprocessor interface - uses any combination of the ts0 national spare bits - a 16-byte message buffer per transmit and receive directions per e1 e1 monitor access for multiplexed applications - select any e1 transmit or receive direction - clock and nrz data brought to bus pins for multiple qe1f- plus alarm indications: programmable alarm generation and consequent actions out of frame out of signaling multiframe out of crc multiframe remote frame alarm remote multiframe alarm all 1's received ts16 ais detection change of frame alignment frame alignment error crc multiframe error signaling multiframe error (ts 16) excessive crc errors slip (transmit and receive) line code violation loss of signal -8 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet error reporting: crc-4 errors framing bit errors far end block errors line code violations count buffer slips error counter roll-over generates a maskable processor interrupt 1-second interrupt input will latch counter values into shadow registers clocks: system clock line clock external clock inputs (2048 kbit/s and 1 hz) flexible rx and tx clock selection slip control: two-frame elastic store for plesiochronous operation (slip buffer) one slip buffer per transmit and receive e1 system test: external boundary scan plus external pin 3-state control hardware and software resets power, package and environment 3.3 volt 5% supply or 5.0 volt 5% supply 128-pin low profile plastic quad flat package power dissipation 125 mw (all channels operational @ 3.3 volt in transmission mode) operating temperature range of -40 to + 85 o c the qe1f- plus has the following feature enhancements relative to the qe1f device (txc-03104) >75% lower power by using 0.5 micron technology (with 3.3 volt power supply) >40% lower power by using 0.5 micron technology (with 5.0 volt power supply) loopbacks per time slot or group of time slots payload loopback corrected fractional e1 support providing gapped clocks for assigned time slots (tx and rx independent assignments) optional in place of signaling highways etsi 300 011 support (g.706-1988 as option to g.706-1991 current support) h.100 frame pulse compliance option to h-mvip (sc bus) all qe1f deviations addressed -9 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet block diagram figure 1. qe1f- plus TXC-03114 block diagram receive slip buffer transmit slip buffer receive framer transmit framer receive signaling transmit signaling hdlc transmit line interface receive line interface framer #1 8 8 8 8 8 8 prbs generator prbs analyzer receive transmit line side system (terminal) side rdata1* rclk1 rsync1 rsigl1*/ tsigl1*/ tdata1* tclk1 tsync1 clkref1 clkref2 prbsool moto dat(7-0) addr(11-0) sel wr rd , rd/wr rdy/dtack int/irq line interface control lo cso config(2-1) t1si rpos1/rldat1 rneg1/rlbpv1/rfs1 lrclk1 tpos1/tldat1 tneg1/tmode1/tfs1 ltclk1 lcs1 lint1 rposn/rldatn rnegn/rlbpvn/rfsn lrclkn tposn/tldatn lsclk/monclk lsdo/mondto lsdi ieee 1149.1 scan i/o: tck tms tdi tdo t rs iotri scan_enb rsyncn rclkn rdatan* rsigln*/ rfe1gcn tsigln*/ tfe1gcn tdatan* tclkn reset sysclk p i/o test access port framer #2 framer #3 framer #4 tnegn/tmoden/tfsn ltclkn lcsn lintn (n=2-4) framer (channel) blocks (4) * note: signaling and data for all four framers are multiplexed on framer 1 signaling and/or data leads for all modes with bit rates above 2 mbit/s. interface rfe1gc1 tfe1gc1 tsyncn (n=2-4) local & remote loopbacks time slot loopbacks -10 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet block diagram description a simplified block diagram of the quad e1 framer- plus (qe1f- plus ) is shown in figure 1. the qe1f- plus consists of the following major blocks: four framer blocks, line interface control, prbs generator, prbs analyzer, microprocessor input/output interface, and test access port. each of the four identical framer blocks consists of the following blocks: receive and transmit line interface blocks, receive and transmit framer blocks, hdlc block, receive and transmit slip buffer blocks, and receive and transmit signaling blocks. the receive and transmit line interface blocks connect each of the four framers to an external line interface transceiver, which performs the liu and clock recovery functions. the interface to the external line interface transceiver can be configured for two interface modes: a dual unipolar (rail) interface or a nrz interface. when the dual unipolar interface mode is selected, input data from the external line interface transceiver is clocked into the qe1f- plus on pins rposn and rnegn using the recovered receive clock present on the lrclkn input pin (where n=1-4 identifies one of the four framers). in the transmit direction, unipolar data is clocked out of the qe1f- plus on pins tposn and tnegn by the transmit line clock present on the ltclkn output pin. for reduced power dissipation in protection switching applications, the ltclkn, tposn, and tnegn pins for the four framers may be forced low, by placing a low on the cso pin. control bits are provided in the memory map which enable the unipolar data to be clocked in and out of the qe1f- plus on either edge of the clocks. for the dual unipolar interface mode, the qe1f- plus provides either a high density bipolar of order 3 (hdb3), or an alternate mark inversion (ami), coder and decoder function, and loss of signal detection. the loss of signal detector meets the requirements specified in the itu-t recommendation g.775. in addi- tion, the detect and recovery intervals for the loss of signal detector circuit are programmable. a sixteen-bit performance counter is provided for each framer, for counting hdb3 coding violation errors. a power-down mode is also provided in the transmit direction. when the nrz interface mode is selected, nrz data is clocked in at the rldatn pin by the recovered received clock present on the lrclkn pin. the nrz data is clocked out of the qe1f- plus on the tldatn pin by the transmit system clock present on the ltclkn pin. control bits are provided in the memory map which enable the nrz data to be clocked in and out of the qe1f- plus on either edge of the clocks. in nrz interface mode, the hdb3 or ami coder and decoder functions are bypassed. however, bipolar violations which are detected in the external line interface transceiver may be clocked into the qe1f- plus on the rlbpvn pin and counted in the associated 16-bit coding violation performance counter. the remote line loopback function for each framer is also implemented in the line interface blocks. the receive framer block for each framer performs two basic functions: frame synchronization and channel associated signaling (cas) multiframe alignment. the frame synchronization circuit has two framing options: frame synchronization based on the frame alignment signal (fas) carried in time slot 0, or frame synchroni- zation based on the frame alignment signal and validation by the crc-4 multiframe alignment signal. the frame synchronizing circuit meets the framing requirements specified in itu-t recommendations g.704 and g.706. the frame synchronization out of frame alarm criteria can be programmed to use 3 or 4 frame align- ment patterns in error, with or without the inclusion of 3 or 4 non-frame alignment patterns in error. framing word errors and crc-4 errors are counted in performance counters. the receive framer block also monitors and detects a remote alarm a-bit (bit 3) in time slot 0 as specified in itu-t recommendation g.704. a non- framing mode can be enabled when the qe1f- plus is configured in the transmission modes. the non-framing mode bypasses the receive framer block and the receive slip buffer. when frame alignment is acquired, the cas multiframe pattern in time slot 16 is detected for alignment. after multiframe alignment is established, the signaling bits are forwarded to the receive signaling block for buffer- ing, microprocessor access, and formatting into the signaling highway data stream. each receive slip buffer controls time slot access and retiming for framer n by using a two-frame receive buffer that can be optionally bypassed in the 2 mbit/s transmission mode. when the receive buffer is enabled, -11 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet received time slots are written into the buffer by recovered receive clock lrclkn, and read out as data (rda- tan) from the slip buffer by the system input clock rclkn. a phase shift between the two clocks is detected in this block and a deletion or repetition of one frame of data (31 time slots, or 30 time slots if time slot 16 is assigned for signaling) is provided when the buffer reaches an almost full or almost empty condition, respec- tively. microprocessor access to the read and write pointers is also provided. channel 0 and channel 16 (when channel 16 is assigned for channel associated signaling) are not affected by a slip. slip alarm indications are provided for the microprocessor. the slip buffer may be recentered by the microprocessor, or automatically. individual time slots can be accessed by the microprocessor for the insertion of system idle or out of service codes. when the receive slip buffer is bypassed, the receive clock (rclkn) and data (rdatan) are provided as outputs, along with a receive sync signal (rsyncn). for channel associated signaling (in time slot 16), a 120-bit signaling buffer is used to store the signaling bits which have been extracted by the receive framer. the signaling bits are stored sequentially in the signaling buffer in the order that they were received. the signaling buffer may be read, frozen and written to by the microprocessor. if signaling is disabled for a particular channel, the abcd signaling bits for that time slot will be frozen in their present states. when a loss of signal or an out of frame condition is detected, the signaling bits are also automatically frozen in their present states. the signaling bit states are held until framing has been recovered. on the terminal side, the system interface interconnects the four framers with the system. for each framer there is a separate receive and transmit highway for the 2 mbit/s transmission and mvip interface modes of operation. the receive highway consists of a data bus (rdatan), a signaling bus (rsigln), a clock (rclkn), and a synchronization signal (rsyncn). the transmit highway consists of a data bus (tdatan), a signaling bus (tsigln), a clock (tclkn), and a synchronization signal (tsyncn). in the 2 mbit/s transmission mode, the system interface operates at 2.048 mhz, with time slots in the data highway, and signaling and alarms on the signaling highway. the receive and transmit system interfaces are synchronized by multiframe pulses that occur at 2-millisecond intervals. sixteen frames are sent on the data and signaling highways within the 2-milli- second period, with each of the sixteen frames consisting of 32 time slots, which correspond to an e1 frame. the receive and transmit slip buffers can be individually bypassed in this mode. the transmission mode is the only mode that supports gapped clocks in place of signaling (rsigln/rfe1gcn and tsigln/tfe1gcn) and permits time slot level remote loopbacks if rsyncn = tsyncn and rclkn = tclkn. when the 2 mbit/s mvip mode is selected, the system interface also consists of receive and transmit data highways. however, the receive and transmit system interfaces are synchronized by pulses occurring at 125- microsecond intervals in this mode. the receive and transmit slip buffers are always enabled in this mode. each frame consists of 32 time slots which correspond to an e1 frame on the data highway. the signaling highway also carries 32 time slots which contain the channel associated signaling states for each channel, the signaling multiframe alignment pattern, the signaling channel spare bits and alarm, plus a time slot that cor- responds to time slot 0 from the e1 frame. the system interface also supports four additional system interface modes: an 8 mbit/s transmission mode, a 16 mbit/s transmission mode, an 8 mbit/s h-mvip/h.100 mode, and a 16 mbit/s pcm highway mode. for these modes, the four framers ? signaling and data frames are either byte- or bit-multiplexed onto the signaling and/or data highway leads that are used by framer 1. all of the six modes are described in detail in the opera- tion section below. the 8 mbit/s transmission mode provides dual receive and transmit highways, which are shared by the four framers. the receive highway consists of a data bus (rdata1), a signaling bus (rsigl1), a clock (rclk1), and a synchronization signal (rsync1). the transmit highway consists of a data bus (tdata1), a signaling bus (tsigl1), a clock (tclk1), and a synchronization signal (tsync1). the data and signaling time slots for each of the four framers are byte-interleaved on the data and signaling highways, starting with framer 1 bit 1 of time slot 0, followed by framer 1 bits 2 through 8 of time slot 0, then framer 2 bits 1 through 8 of time slot 0, and so on, ending with framer 4 bits 1 through 8 of time slot 31. in this mode, the separate data and signaling highways operate at 8.192 mbit/s. however, the clock rate is 16.384 mhz. the receive and transmit system interfaces are synchronized by multiframe pulses that occur at 2-millisecond intervals. the receive and trans- -12 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet mit slip buffers must be enabled in each of the framers. within the 2-millisecond period, the 32 data and signal- ing time slots for each of the four framers are repeated 16 times. the 16 mbit/s transmission mode provides single receive and transmit highways which are shared by the four framers. the receive highway consists of a data bus (rdata1), a clock (rclk1), and a synchronization signal (rsync1). the transmit highway consists of a data bus (tdata1), a clock (tclk1), and a synchronization signal (tsync1). the data and signaling time slots for each of the four framers are bit-interleaved on the data highway, starting with framer 1 data time slot 0 bit 1, followed by framer 1 signaling time slot 0 bit 1, framer 2 data time slot 0 bit 1, framer 2 signaling time slot 0 bit 1, and so on, and ending with framer 4 signaling time slot 31 bit 8. in this mode, the single data highway operates at 16.384 mbit/s. the receive and transmit system interfaces are synchronized by pulses that occur at 2-millisecond intervals. the receive and transmit slip buff- ers must be enabled in each of the framers. within the 2-millisecond period, the 32 data and signaling time slots for each of the four framers are repeated 16 times. the 8 mbit/s h-mvip/h.100 mode provides dual receive and transmit highways, which are shared by the four framers. the receive highway consists of a data bus (rdata1), a signaling bus (rsigl1), a clock (rclk1), and a synchronization signal (rsync1). the transmit highway consists of a data bus (tdata1), a signaling bus (tsigl1), a clock (tclk1), and a synchronization signal (tsync1). the data and signaling time slots for each of the four framers are byte-interleaved on the data and signaling highways, starting with framer 1 bit 1 of time slot 0, followed by framer 1 bits 2 through 8 of time slot 0, then framer 2 bits 1 through 8 of time slot 0, and so on, ending with framer 4 bits 1 through 8 of time slot 31. in this mode, the separate data and signaling highways operate at 8.192 mbit/s. however, the clock rate is 16.384 mhz. the receive and transmit system interfaces are synchronized by pulses that occur at 125-microsecond intervals. the receive and transmit slip buffers must be enabled in each of the framers. the 16 mbit/s pcm highway mode provides single receive and transmit highways which are shared by the four framers. the receive highway consists of a data bus (rdata1), a clock (rclk1), and a synchronization signal (rsync1). the transmit highway consists of a data bus (tdata1), a clock (tclk1), and a synchronization signal (tsync1). the data and signaling time slots for each of the four framers are bit-interleaved on the data highway, starting with framer 1 data time slot 0 bit 1, followed by framer 1 signaling time slot 0 bit 1, framer 2 data time slot 0 bit 1, framer 2 signaling time slot 0 bit 1, and ending with framer 4 signaling time slot 31 bit 8. in this mode, the single data highway operates at 16.384 mbit/s. the receive and transmit system interfaces are synchronized by pulses that occur at 125-microsecond intervals. the receive and transmit slip buffers must be enabled in each of the framers. for the framer 1 terminal side interface, multiplexers are used to distribute the data and signaling highways from the 8 mbit/s and 16 mbit/s transmission modes, the 8 mbit/s h-mvip/h.100 mode, and the 16 mbit/s pcm highway mode, to the four individual framers. for the 2 mbit/s transmission mode, and the 2 mbit/s mvip mode, separate data and signaling highways are used for the four framers. a transmit buffer is provided to absorb low speed jitter in the transmit data. each transmit slip buffer block controls time slot access and retiming for the framer by using a two-frame buffer that can be optionally bypassed in the transmission modes. when the transmit buffer is enabled, transmit time slots are written into the buffer by the transmit system clock (tclkn), and they are read out from the buffer by the receive clock (lrclkn), local oscillator (lo), or transmit system clock (tclkn). a phase shift between the two clocks is detected in this block, and a deletion or repetition of one frame of data (i.e., 31 time slots, or 30 time slots if time slot 16 is assigned for signaling) is provided when the buffer reaches an almost full or almost empty con- dition, respectively. microprocessor access to the read and write pointers is also provided. buffer alarm indica- tions are also provided. the slip buffer may be recentered by the microprocessor, or automatically. individual time slots can be accessed by the microprocessor for the insertion of system idle or out of service codes. the transmit framer block forms the frame (with or without the crc multiframe) with time slots read from the transmit slip buffer block, and signaling information from the transmit signaling block. the international bits from the signaling highway are inserted into time slot 0 via a buffer when the framing mode is selected. the national bits in time slot 0 can be inserted from the hdlc block or from the system interface via a buffer. the -13 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet crc-4 is calculated as specified in itu-t recommendation g.706 and inserted in time slot 0. the remote alarm indication for time slot 0 is inserted as a result of a receiver loss of frame alignment alarm, or by the microprocessor, or via the signaling highway (tsigln). a single frame bit error, or crc-4 error, can be gener- ated for test purposes. the transmit framer and transmit slip buffer can be bypassed if the unframed mode of operation is selected in the 2 mbit/s transmission mode. each framer has a full duplex hdlc block. the hdlc block can be configured to send and receive messages using any of the five spare bits reserved for national use (sa bits) in time slot 0 in alternating frames. a 16- byte fifo is provided in each direction. interrupt and status alarm support is provided to facilitate fifo servic- ing for long messages. the hdlc controller supports zero bit stuffing/destuffing, itu-t crc generation/ checking, flag generation/detection, abort generation/detection, start of frame detection, end of frame detec- tion, and fifo underflows and overflows. the line interface control block provides a serial port for communicating with an external line interface trans- ceiver. this allows the system microprocessor to control the transceiver through the qe1f- plus . the interface consists of a data output pin (lsdo), clock output pin (lsclk), and a data input pin (lsdi). these signals are shared between all of the transceivers. each transceiver is selected by the qe1f- plus , using individual chip select output signals (lcsn ). in addition, a general purpose input pin (lintn) can be used to generate a maskable interrupt. the test access port block includes a five-pin test access port (tap) that conforms to the ieee 1149.1 stan- dard. this test access port block provides external boundary scan to read and write the qe1f- plus input and output pins from the tap for board and component testing. in addition, a four-byte read only memory location is provided for reading the jedec manufacturer id, qe1f- plus part number, and version number of the part. to assist in testing, built-in pseudo random binary sequence (prbs) generator and analyzer blocks are pro- vided. the prbs generator and analyzer support the 2 15 -1 bit pseudo random binary sequence which is specified in the itu-t recommendation o.151. each framer may select the prbs generator and analyzer. the output of the analyzer is provided on pin prbsool. the prbs framed mode is selected by writing a 1 to bit 6 in register 013h and is intended for use as a self-test feature. in this mode, the prbs generator and ana- lyzer can only communicate and frame up within the framer itself. the qe1f- plus also provides local loop- back, remote line loopback, remote time slot loopback and payload remote loopback options for each framer. the qe1f- plus can be configured to operate with either intel or motorola compatible microprocessors via the microprocessor input/output interface block. interrupt capability is provided with global and individual framer mask bits. an option is provided in software which permits the interrupt polarity to be inverted. an external sys- tem clock is used to run the internal state machines. -14 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet pin diagram figure 2. qe1f- plus TXC-03114 pin diagram addr2 addr3 addr4 addr5 addr6 addr7 addr8 addr9 addr10 dat0 dat1 gnd addr11 vdd dat2 dat3 dat4 dat5 gnd dat6 dat7 int/irq sel wr gnd rd or rd/wr rdata1 t1si lo config2 config1 gnd vdd clkref1 prbsool iotri scan_enb gnd cso gnd tck tdo tdi trs vdd tms lsdi lsclk/monclk rpos1/rldat1 rneg1/rlbpv1/rfs1 lsdo/mondto lint1 addr1 addr0 sysclk moto lcs4 lt c l k 4 tneg4/tmode4/tfs4 tpos4/tldat4 lrclk4 rpos4/rldat4 lint4 gnd rneg4/rlbpv4/rfs4 vdd lcs3 lt c l k 3 tneg3/tmode3/tfs3 tpos3/tldat3 gnd lrclk3 rneg3/rlbpv3/rfs3 lint3 vdd ltclk2 rpos3/rldat3 lcs2 tneg2/tmode2/tfs2 tpos2/tldat2 lrclk2 gnd rneg2/rlbpv2/rfs2 rpos2/rldat2 lint2 lcs1 tneg1/tmode1/tfs1 lrclk1 lt c l k 1 tpos1/tldat1 re set clkref2 tsync4 tclk4 tsigl4/tfe1gc4 tdata4 rsync4 rclk4 rsigl4/rfe1gc4 tsync3 tclk3 rdy/dtack rdata4 vdd tsigl3/tfe1gc3 tdata3 rsync3 rclk3 rsigl3/rfe1gc3 gnd rdata3 tclk2 vdd tdata2 tsync2 tsigl2/tfe1gc2 rsync2 rclk2 rsigl2/rfe1gc2 gnd rdata2 tsync1 tclk1 tsigl1/tfe1gc1 rsync1 rsigl1/rfe1gc1 tdata1 rclk1 96 95 94 93 92 91 90 83 82 81 80 79 78 77 70 69 68 67 66 65 45 46 47 49 50 51 58 59 60 61 62 63 64 76 75 74 73 72 71 89 88 87 86 85 84 102 101 100 99 98 97 52 53 54 55 56 57 39 40 41 42 43 44 122 121 120 119 118 117 116 109 108 107 106 105 104 103 115 114 113 112 111 110 128 127 126 125 124 123 48 1 2 3 4 5 6 7 8 9 10 11 12 13 20 21 22 23 24 25 26 33 34 35 36 37 38 14 15 16 17 18 19 27 28 29 30 31 32 14 (top view) pin diagram qe1f- plus TXC-03114 -15 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet pin descriptions power supply and ground * note: i = input; o = output; p = power; t=tri-state. line interface signals symbol pin no. i/o/p* type name/function vdd 14, 25, 45, 57, 78, 89, 116 p power supply: +3.3 or +5 volt supply voltage, 5%. gnd 20, 30, 44, 47, 52, 73, 84, 94, 111, 121, 124 p ground: 0 volt reference. symbol pin no. i/o/p type * name/function ** rposn/ rldatn (n=4-1) 91 81 71 63 icmos receive unipolar positive signal input: when control bit rail (bit 7 in x00h) is a 1, the dual unipolar mode is selected, and the rposn pin carries the receive positive rail input signal. rposn is high whenever a positive pulse is received by the external line interface transceiver. receive line (nrz) data input: when control bit rail (bit 7 in x00h) is a 0, the nrz mode is selected, and the rldatn pin carries the receive nrz data input signal. rldatn is normally active high whenever a positive or negative pulse is received by the external line interface transceiver. when control bit rxnrzp (bit 0 in register x01h) is a 1, the qe1f- plus accepts an inverted data signal and rldatn is active low. rnegn/ rlbpvn/ rfsn (n=4-1) 92 82 72 64 icmos receive unipolar negative signal input: when control bit rail (bit 7 in x00h) is a 1, the dual unipolar mode is selected, and the rnegn pin carries the receive negative rail input signal. rnegn is high whenever a negative pulse is received by the external line interface transceiver. external receive bipolar violation indication input: when control bit rail (bit 7 in x00h) is a 0 and the fast sync option is not selected (control bit rxfs, bit 1 in x06h, is a 0), the rlbpvn pin provides an input for indications of external bipolar violations detected in the external line interface transceiver. a high indicates a bipolar violation, and increments the internal 16-bit coding violation counter once on a clock cycle. a bipolar violation is clocked in on rising edges of the receive line clock lrclkn. receive fast sync: when control bit rail (bit 7 in x00h) is a 0 and the fast sync mode is selected (control bit rxfs, bit 1 in x06h, is 1), this pin is used for a fast sync feature. a pulse on this pin is interpreted as identifying bit 256 of the last frame of the multiframe. * note: see input, output and i/o parameters section for type definitions. ** note: the value of x (hex.), which is used as the ms digit of register addresses for per channel memory bits, such as x01h, is equal to the value of n (dec.) used in pin symbols when both relate to the same channel or framer (number n, where n=1-4). register addresses such as 006h, which have 0 as the ms digit instead of x, contain bits that are common to all four framers. -16 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet lrclkn (n=4-1) 93 83 74 65 icmos receive line clock: an input for the 2048 khz recovered clock from the external line interface transceiver. control bit rxcp (bit 6 in x01h) determines the clock edge on which the receive line signals rposn/ rnegn and rldatn are to be clocked in (1 for rising edge). this pin is active only in the nrz mode. tposn/ tldatn (n=4-1) 95 85 75 66 o cmos 2ma transmit unipolar positive signal output: when control bit rail (bit 7 in x00h) is a 1, the dual unipolar mode is selected, and the tposn pin carries the transmit positive rail output signal. tposn is high when- ever a positive pulse is to be transmitted by the external line interface transceiver. transmit line (nrz) data output: when control bit rail (bit 7 in x00h) is a 0, the nrz mode is selected, and the tldatn pin carries the transmit nrz data output signal. tldatn is normally active high whenever a positive or negative pulse is to be transmitted by the exter- nal line interface transceiver. when control bit txnrzp (bit 5 in register x01h) is a 1, the data output tldatn is inverted and it is active low. tnegn/ tmoden/ tfsn (n=4-1) 96 86 76 67 o cmos 2ma transmit unipolar negative signal output: when control bit rail (bit 7 in x00h) is a 1, the dual unipolar mode is selected, and the tnegn pin carries the transmit negative rail output signal. tnegn is high whenever a negative pulse is to be transmitted by the external line interface transceiver. transmit mode general purpose output: when control bit rail (bit 7 in x00h) is a 0 and the fast sync mode is not selected (control bit txfs, bit 0 in x06h, is a 0), the state written into bit be (bit 6 in x00h) is clocked out on rising edges of the transmit line clock ltclkn. transmit fast sync: when control bit rail (bit 7 in x00h) is a 0 and the fast sync mode is selected (control bit txfs, bit 0 in x06h is a 1), this pin is used for a fast sync feature. a pulse is sent on this pin every 2 ms, corresponding to bit 256 of the last frame in the multiframe. lt c l k n (n=4-1) 97 87 77 68 o cmos 2ma transmit line clock: a 2048 khz clock output. control bit txcp (bit 7 in x01h) determines the clock edge on which the transmit line signals tposn/tnegn and tldatn are to be clocked out (1 for rising edge). symbol pin no. i/o/p type * name/function ** * note: see input, output and i/o parameters section for type definitions. ** note: the value of x (hex.), which is used as the ms digit of register addresses for per channel memory bits, such as x01h, is equal to the value of n (dec.) used in pin symbols when both relate to the same channel or framer (number n, where n=1-4). register addresses such as 006h, which have 0 as the ms digit instead of x, contain bits that are common to all four framers. -17 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet line interface control signals symbol pin no. i/o/p type name/function lintn (n=4-1) 90 80 70 62 icmos general purpose interrupt input port: when enabled by control bit lie (bit 1 in x00h) being set to 1, the signal on this pin is logically or-gated with the internal loss of signal indication to cause a loss of signal alarm and (if enabled) an interrupt. control bit lpol (bit 0 in x00h) selects the input sense of this pin (1 for active low). lcs n (n=4-1) 98 88 79 69 o cmos 2ma line interface transceiver chip select: an active low signal that enables communications in both directions between the external line interface transceiver for channel n and the qe1f- plus . lsclk/ monclk 61 o(t) cmos 2ma line interface transceiver clock signal: the clock for the transceiver is enabled when the config2 pin (pin 42) is low. this clock is shared between the four external trans- ceivers. it is used to clock input data, and output data, between the external line interface transceiver and the qe1f- plus . output data (lsdo) is clocked out of the qe1f- plus on falling edges of this clock. input data (lsdi) is clocked into the qe1f- plus on rising edges of this clock. this clock is derived from the signal at the lo pin (pin 41). monitor clock signal: the monitor feature is enabled when the config2 pin (pin 42) is high. the monclk pin provides either a receive or transmit nrz clock. the clock in this mode can be tri-stated by writing a 0 to control bit esp/emon (bit 4 in 013h). lsdo/ mondto 60 o(t) cmos 2ma line interface transceiver data output signal: the out- put data signal for the transceivers is enabled when the config2 pin (pin 42) is low. the output data signal is shared between the four transceivers. monitor data signal: the monitor feature is enabled when the config2 pin (pin 42) is high. the mondto pin provides either a nrz receive or transmit data signal. this pin can be tri-stated in this mode by writing a 0 to control bit esp/emon (bit 4 in 013h). lsdi 59 i cmos line interface transceiver data input signal: the input data signal from the transceivers is enabled when the config2 pin (pin 42) is low. the input data signal is shared between the four transceivers. -18 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet clock reference signals system interface signals symbol pin no. i/o/p type name/function clkref1 46 o(t) cmos 2ma clock reference 1: this clock reference output is enabled when control bit enref1 (bit 3 in 019h) is a 1. the clock reference signal can be either a 2048 khz clock or an 8 khz clock. when control bit 2048khz (bit 4 in 019h) is a 1, the 2048 khz reference is selected. the framer from which the clock is derived is determined by selec- tion bits cr1s1 and cr1s0 (bits 1 and 0 in 019h). this pin is forced low when a loss of signal alarm occurs for the framer selected. clkref2 2 o(t) cmos 2ma clock reference 2: this clock reference output is enabled when control bit enref2 (bit 5 in 019h) is a 1. the clock reference signal can be either a 2048 khz clock or an 8 khz clock. when control bit 2048khz (bit 4 in 019h) is a 1, the 2048 khz reference is selected. the framer from which the clock is derived is determined by selec- tion bits cr2s1 and cr2s0 (bits 7 and 6 in 019h). this pin is forced low when a loss of signal alarm occurs for the framer selected. symbol pin no. i/o/p type name/function tsyncn (n=4-1) 3 12 22 32 icmos transmit sync pulse : this signal is used to synchronize both the frame sync and signaling multiframe sync counters within a qe1f- plus framer and is sourced by the system. the following table is a summary of the sync pulse characteristics used for the various sys- tem interfaces. interface width polarity period lead used 2 mbit/s trans 1 clk cyc high 2 ms tsyncn 8 mbit/s trans 2 clk cyc high 2 ms tsync1 16 mbit/s trans 1 clk cyc high 2 ms tsync1 2 mbit/s mvip 1 clk cyc low 125 stsyncn 8 mbit/s h-mvip 4 clk cyc low 125 stsync1 8 mbit/s h.100 2 clk cyc low 125 stsync1 16 mbit/s pcm 1 clk cyc high 125 stsync1 note: the sync pulse is also programmable with respect to the trans- mit data highway. tclkn (n=4-1) 4 13 23 33 icmos trans mit clock : this clock is sourced from the system. it is used to clock in the tsyncn, tsigln, and tdatan signals from the system. the following table is a summary of the clock rates and clock transi- tions used for clocking in data (d), signaling (s), and the sync. clk in clk in interface rate d/s sync lead used 2 mbit/s trans 2.048 mhz pos. pos. tclkn 8 mbit/s trans 16.384 mhz pos. pos. tclk1 16 mbit/s trans 16.384 mhz pos. pos. tclk1 2 mbit/s mvip 2.048 mhz neg. pos. tclkn 8 mbit/s h-mvip/h.100 16.384 mhz pos. neg. tclk1 16 mbit/s pcm 16.384 mhz pos. pos. tclk1 -19 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet tdatan (n=4-1) 6 16 26 35 icmos transmit data highway input: this lead carries the data time slots from the system interface to the qe1f- plus . the following table is a summary of the transmit data highway format. i nterface format 2 mbit/s trans e1 frame repeated 16 times on tdatan 8 mbit/s trans four e1 frames repeated 16 times, byte-interleaved on tdata1 16 mbit/s trans four e1 and signaling frames repeated 16 times, bit-interleaved on tdata1 2 mbit/s mvip e1 frame on tdatan 8 mbit/s h-mvip/h.100 four e1 frames, byte-interleaved on tdata1 16 mbit/s pcm four e1 and signaling frames, bit-inter- leaved on tdata1 tsigln/ tfe1gcn (n=4-1) 5 15 24 34 i/o cmos 2ma transmit signaling highway input: this lead carries from the sys- tem the signals that represent the international bits, national bits, and remote alarm associated with time slot 0, signaling information, and system alarm information, according to the table given below. i nterface format 2 mbit/s trans 32 time slots repeated 16 times on tsigln 8 mbit/s trans 32 time slots for 4 framers repeated 16 times, byte-interleaved on tsigl1 16 mbit/s trans not used 2 mbit/s mvip 32 time slots on tsigln 8 mbit/s h-mvip/h.100 32 time slots for 4 framers repeated 16 times byte-interleaved on tsigl1 16 mbit/s pcm not used transmit fractional e1 gapped clock output: the transmit frac- tional e1 gapped clock feature is enabled when the config1 pin is low, control bits hmvip and mtp16m (bits 2 and 1 in register 006h) are both set to 0 (2 mbit/s transmission mode) and control bit fe1m (bit 0 in register x02h) is written with a 1. a gapped clock is provided on the pin for the fractional e1 channel(s) selected. one or more time slots may be selected by writing a 1 to control bits tfts31- tfts0 in registers x3ch-x3fh. the gapped clock has the same phase as the tclkn clock. symbol pin no. i/o/p type name/function -20 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet rsyncn (n=4-1) 7 17 27 36 i/o cmos 2ma receive sync pulse: this signal is used to synchronize external system circuitry from the qe1f- plus . the following table is a sum- mary of the sync pulses used for the various system interfaces. i nterface width polarity period lead used 2 mbit/s trans 1 clk cyc high 2 ms rsyncn 8 mbit/s trans 2 clk cyc high 2 ms rsync1 16 mbit/s trans 1 clk cyc high 2 ms rsync1 2 mbit/s mvip 1 clk cyc low 125 s rsyncn 8 mbit/s h-mvip 4 clk cyc low 125 s rsync1 8 mbit/s h.100 2 clk cyc low 125 s rsync1 16 mbit/s pcm 1 clk cyc high 125 srsync1 note: in the 2 mbit/s transmission mode, the qe1f- plus can source the sync pulse and clock. the sync pulse is also programmable with respect to the receive data highway. rclkn (n=4-1) 8 18 28 37 i/o cmos 2ma receive clock: this clock is used to clock the rdatan, rsigln, and rsyncn signals from the system or (for rsyncn) into the sys- tem. the following table is a summary of the clock rates and clock transitions used for clocking data (d), signaling (s), and the sync pulse. clk out clk in i nterface rate d/s sync lead used 2 mbit/s trans 2.048 mhz neg. pos. rclkn 8 mbit/s trans 16.384 mhz neg. pos. rclk1 16 mbit/s trans 16.384 mhz neg. pos. rclk1 2 mbit/s mvip 2.048 mhz pos. pos. rclkn 8 mbit/s h-mvip/h.100 16.384 mhz neg. pos. rclk1 16 mbit/s pcm 16.384 mhz neg. pos. rclk1 note: in the 2 mbit/s transmission mode, rsyncn is clocked out on negative clock transitions when the sync pulse is an output. rdatan (n=4-1) 11 21 31 39 o cmos 2ma for n=4-2 cmos 8ma for n=1 receive data highway output: this lead carries the time slots from the qe1f- plus to the system. the following table is a summary of the receive data highway format. i nterface format 2 mbit/s trans e1 frame repeated 16 times on rdatan 8 mbit/s trans four e1 frames repeated 16 times, byte-interleaved on rdata1 16 mbit/s trans four e1 and signaling frames repeated 16 times, bit-interleaved on rdata1 2 mbit/s mvip e1 frame on rdatan 8 mbit/s h-mvip/h.100 four e1 frames, byte-interleaved on rdata1 16 mbit/s pcm four e1 and signaling frames, bit-interleaved on rdata1 symbol pin no. i/o/p type name/function -21 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet other signals rsigln/ rfe1gcn (n=4-1) 10 19 29 38 o cmos 2ma for n=4-2 cmos 8ma for n=1 receive signaling highway output: this lead carries to the sys- tem the signals that represent the international bits, national bits, and remote alarm associated with time slot 0, signaling information, and system alarm information, according to the table given below. interfac e f ormat 2 mbit/s trans 32 time slots repeated 16 times on rsigln 8 mbit/s trans 32 time slots for 4 framers repeated 16 times, byte-interleaved on rsigl1 16 mbit/s trans not used 2 mbit/s mvip 32 time slots on rsigln 8 mbit/s h-mvip/h.100 32 time slots for 4 framers repeated 16 times, byte-interleaved on rsigl1 16 mbit/s pcm not used receive fractional e1 gapped clock output: the received frac- tional e1 gapped clock feature is enabled when the config1 pin is low, control bits hmvip and mtp16m (bits 2 and 1 in register 006h) are both set to 0 (2 mbit/s transmission mode) and control bit fe1m (bit 0 in register x02h) is written with a 1. a gapped clock is provided on this pin for the fractional e1 channel(s) selected. one or more time slots may be selected by writing a 1 to control bits rfts31- rfts0 in registers x38h-x3bh. the gapped clock has the same phase as the rclkn clock. lo 41 icmos local oscillator input: this independent 2048 khz 50 ppm (50 10)% duty cycle clock is an alternate clock source for the transmit line clock (ltclkn), and for clocking out data from the slip buffer. this clock is selected as the transmit clock source when control bits txc1 and txc0 (bits 7 and 6 in x02h) are both set to 0. on detec- tion of loss of signal, this clock is substituted for the receive line clock (lrclkn) which becomes rclkn when control bit rxc (bit 5 in register x02h) is set to a 1. this clock is required for generating lsclk (pin 61) and the prbs generator function. when used for the prbs generator, the input lo must be synchronous and in phase with tclkn. symbol pin no. i/o/p type name/function t1si 40 i cmos one second shadow register signal : a positive pulse occurring every second which operates the latched perfor- mance counters and shadow registers when the shadow register feature is enabled. the shadow register feature is enabled when a 1 is written to control bit enpmfm (bit 3 in 006h). symbol pin no. i/o/p type name/function -22 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet boundary scan config2 42 i cmos configuration 2 select pin : a low enables the line control interface for communications between the qe1f- plus and the external line interface transceivers. a high disables the line control interface, and configures clock and data pins for a monitor interface. the selection is common to all four framers. config1 43 i cmos configuration 1 select pin : a low configures the qe1f- plus for the transmission modes of operation (2, 8, and 16 mbit/s) at the system interface. a high configures the qe1f- plus for the 2 mbit/s mvip, the 8 mbit/s h-mvip/ h.100, and the 16 mbit/s pcm highway modes of opera- tion at the system interface. the selection is common to all four framers. cso 49 i cmos power down : an active low on this pin forces the transmit clock (ltclkn), and the transmit unipolar leads (tposn and tnegn) for rail data output signals, of all four framers to the active low state for protection switching purposes. prbsool 48 o cmos 2ma prbs out of lock: enabled only in the 2 mbit/s transmis- sion mode and when control bit prbsen (bit 5 in 013h) is a 1. a high indicates the analyzer is out of lock. this pin is low when lock is acquired or when this feature is disabled. iotri 50 i ttl high z state: an active low placed on this pin forces all output pins (except tdo) to a high impedance state for test purposes. this pin must be held high for normal opera- tion. scan_enb 51 i cmos transwitch test pin: this pin is used for manufacturing tests only and must be held low for normal operation. symbol pin no. i/o/p type name/function tck 53 i ttl ieee 1149.1 test port serial scan clock: this clock is used to shift data in from pin tdi on rising edges, and to shift data out on pin tdo on falling edges. the maximum clock frequency is 10 mhz. tms 58 i ttlp ieee 1149.1 test port mode select: this signal is clocked in on rising edges of the clock tck, and is used to place the test access port controller into various states as defined in the ieee 1149.1 standard. this pin must be high for normal framer operation. tdi 55 i ttlp ieee 1149.1 test port serial scan data in: serial test instructions and data are clocked in to this pin on rising edges of clock tck. symbol pin no. i/o/p type name/function -23 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet microprocessor interface tdo 54 o (t) ttl 4ma ieee 1149.1 test port serial scan data out: serial test instructions and data are clocked out of this pin on falling edges of clock tck. when inactive (i.e., trs is low), this output is forced to the high impedance state. trs 56 i ttlp ieee 1149.1 test port reset pin: this pin must either be held low, asserted low, or asserted low then high (pulsed low, minimum 10 ns) to asynchronously reset the test access port (tap) controller. failure to do so may cause the tap controller to take control of the qe1f- plus output pins. symbol pin no. i/o/p type name/function moto 99 i ttl motorola/intel processor select: this pin defines the operating mode of the microprocessor input/output inter- face. when it is high, motorola (m) mode is selected. when it is low, intel (i) mode is selected. addr(11-0) 113, 112 110-101 i ttl address bus (motorola/intel buses): these pins are address line inputs that are used for accessing a register location for a read/write cycle. high is logic 1. dat(7-0) 123, 122, 120-117, 115, 114 i/o (t) ttl 8ma data bus: bidirectional data lines used for transferring data. high is logic 1. sel 127 i ttlp select: a low enables data transfers between the micro- processor and the qe1f- plus during a read/write cycle. r d or rd/w r 126 i ttl read (i mode) or read/write (m mode): intel mode - an active low signal generated by the micro- processor for reading the qe1f- plus register locations. motorola mode - an active high signal generated by the microprocessor for reading the qe1f- plus register loca- tions. an active low signal is used to write to qe1f- plus register locations. wr 128 i ttl write (i mode): intel mode - an active low signal generated by the micro- processor for writing to the qe1f- plus register locations. motorola mode - not used (should be set high). symbol pin no. i/o/p type name/function -24 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet rdy/dtack 9o(t)ttl 8ma ready (i mode) or data transfer acknowledge (m mode): intel mode - a high is an acknowledgment from the addressed register location that the transfer can be com- pleted. a low indicates that the qe1f- plus cannot com- plete the transfer cycle, and microprocessor wait states must be generated. motorola mode - during a read bus cycle, a low signal indi- cates the information on the data bus is valid. during a write bus cycle, a low signal acknowledges the acceptance of data. this lead is tri-stated after the low signal. int/irq 125 o ttl 4ma interrupt: intel mode - a high on this output pin signals an interrupt request to the microprocessor. motorola mode - a low on this output pin signals an inter- rupt request to the microprocessor. the interrupt sense is inverted when a 1 is written to con- trol bit ipol (bit 4 in 006h). reset 1 i ttlp reset: a low placed on this pin resets the qe1f- plus . the reset must be placed on this pin after the clocks become stable, and must have a minimum duration of 10 cycles of the sysclk system clock. sysclk 100 i ttl system clock: this asynchronous clock is used by the qe1f- plus to run the internal state machines and counters. the nominal frequency of this clock is 19-22 mhz with a duty cycle of (50 10)%. when recovered receive line clock (lrclkn) is used for system side receive clock (rclkn) by setting control bit rxc to a 1, the nomi- nal frequency of this clock is 19-22 mhz with a duty cycle of (50 10)%. when the qe1f- plus is used in a gapped or jittered clock situation, the sysclk minimum frequency must guarantee at least 9 rising edges of sysclk to occur between any two consecutive rising or falling edges of any particular lrclkn. the following table can be used to determine the required minimum sysclk frequency. symbol pin no. i/o/p type name/function lrclkn minimum t cyc (ns) sysclk minimum frequency (mhz) 480 19 456 20 435 21 -25 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet absolute maximum ratings and environmental limitations notes: 1. conditions exceeding the min or max values may cause permanent failure. exposure to conditions near the min or max values for extended periods may impair device reliability. 2. pre-assembly storage in non-drypack conditions is not recommended. please refer to the instructions on the "caution" label on the drypack bag in which devices are supplied. 3. v in may not exceed the actual operating supply voltage ( v dd ) by more than 0.5 volt. thermal characteristics power requirements for v dd = 5 volt power requirements for v dd = 3.3 volt parameter symbol min max unit conditions supply voltage v dd -0.3 +7.0 v note 1 dc input voltage v in -0.5 v dd + 0.5 v note 1,3 storage temperature range t s -55 150 o cnote 1 ambient operating temperature t a -40 85 o c 0 ft/min linear airflow component temperature x time ti 270 x 5 o c x s note 1 moisture exposure level me 5 level per eia/jedec jesd22-a112-a relative humidity, during assembly rh 30 60 % note 2 relative humidity, in-circuit rh 0 100 % non-condensing esd classification esd 2000 v per mil-std-883d method 3015.7 parameter min typ max unit test conditions thermal resistance: junction to ambient 24.8 o c/w 0 ft/min linear airflow. parameter min typ max unit test conditions v dd 4.75 5.0 5.25 v power dissipation, p dd , with all channels operating: 300 mw sysclk = 19 mhz, 25 o c ambient, bit rate = 2 mbit/s, with 10 pf output load 440 mw sysclk = 22 mhz, 85 o c ambient, bit rate = 2 mbit/s, with 10 pf output load parameter min typ max unit test conditions v dd 3.15 3.3 3.45 v power dissipation, p dd , with all channels operating: 125 mw sysclk = 19 mhz, 25 o c ambient, bit rate = 2 mbit/s, with 10 pf output load 165 mw sysclk = 22 mhz, 85 o cambient, bit rate = 2 mbit/s, with 10 pf output load -26 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet input, output and i/o parameters input parameters for 5 volt operation input parameters for cmos at v dd = 5 volt input parameters for ttl at v dd =5 volt input parameters for ttlp at v dd =5 volt note: input has a 9k (nominal) internal pull-up resistor. parameter min typ max unit test conditions v ih 3.15 v 4.75 < v dd < 5.25 v il 1.65 v 4.75 < v dd < 5.25 input leakage current 10 av dd = 5.25 input capacitance 3.5 pf parameter min typ max unit test conditions v ih 2.0 v 4.75 < v dd < 5.25 v il 0.8 v 4.75 < v dd < 5.25 input leakage current 10 av dd =5.25 input capacitance 3.5 pf parameter min typ max unit test conditions v ih 2.0 v 4.75 < v dd < 5.25 v il 0.8 v 4.75 < v dd < 5.25 input leakage current 0.5 1.4 ma v dd = 5.25; input = 0 volt input capacitance 3.5 pf -27 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet output parameters for 5 volt operation output parameters for cmos2ma/cmos8ma at v dd =5 volt output parameters for ttl4ma at v dd =5 volt output parameters for ttl8ma at v dd =5 volt parameter min typ max unit test conditions v oh v dd - 0.5 v v dd = 4.75; i oh = -2.0/-8.0 v ol 0.4 v v dd = 4.75; i ol = 2.0/8.0 i ol 2.0/8.0 ma i oh -2.0/-8.0 ma t rise 10 ns c load = 15 pf t fall 10 ns c load = 15 pf leakage tri-state 10 a 0 to 5.25 v input parameter min typ max unit test conditions v oh 2.4 v dd vv dd = 4.75; i oh = -2.0 v ol 0.4 v v dd = 4.75; i ol = 4.0 i ol 4.0 ma i oh -2.0 ma t rise 8nsc load = 15 pf t fall 5nsc load = 15 pf parameter min typ max unit test conditions v oh 2.4 v dd vv dd = 4.75; i oh = -4.0 v ol 0.4 v v dd = 4.75; i ol = 8.0 i ol 8.0 ma i oh -4.0 ma t rise 10 ns c load = 25 pf t fall 5nsc load = 25 pf -28 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet input/output parameters for 5 volt operation input/output parameters for cmos2ma at v dd =5 volt input/output parameters for ttl8ma (slew rate controlled) at v dd =5 volt parameter min typ max unit test conditions v ih 3.15 v 4.75 < v dd < 5.25 v il 1.65 v 4.75 < v dd < 5.25 input leakage current 10 av dd = 5.25 input capacitance 7.0 pf v oh v dd - 0.5 v v dd = 4.75; i oh = -2.0 v ol 0.4 v v dd = 4.75; i ol = 2.0 i ol 2.0 ma i oh -2.0 ma t rise 10 ns c load = 15 pf t fall 10 ns c load = 15 pf leakage tri-state 10 a 0 to 5.25 v input parameter min typ max unit test conditions v ih 2.0 v 4.75 < v dd < 5.25 v il 0.8 v 4.75 < v dd < 5.25 input leakage current 10 av dd = 5.25 input capacitance 7.0 pf v oh 2.4 v dd vv dd = 4.75; i oh = -4.0 v ol 0.4 v v dd = 4.75; i ol = 8.0 i ol 8.0 ma i oh -4.0 ma t rise 10 ns c load = 25 pf t fall 5nsc load = 25 pf -29 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet input parameters for 3.3 volt operation input parameters for cmos at v dd = 3.3 volt input parameters for ttl at v dd = 3.3 volt input parameters for ttlp at v dd = 3.3 volt note: input has a 9k (nominal) internal pull-up resistor. parameter min typ max unit test conditions v ih 2.2 v dd + 0.5 v 3.15 < v dd < 3.45 v il 1.0 v 3.15 < v dd < 3.45 input leakage current 10 av dd = 3.45 input capacitance 3.5 pf parameter min typ max unit test conditions v ih 2.0 v dd + 0.5 v 3.15 < v dd < 3.45 v il 0.8 v 3.15 < v dd < 3.45 input leakage current 10 av dd = 3.45 input capacitance 3.5 pf parameter min typ max unit test conditions v ih 2.0 v dd + 0.5 v 3.15 < v dd < 3.45 v il 0.8 v 3.15 < v dd < 3.45 input leakage current 0.5 1.4 ma v dd = 3.45; input = 0 volt input capacitance 3.5 pf -30 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet output parameters for 3.3 volt operation output parameters for cmos2ma/cmos8ma at v dd = 3.3 volt output parameters for ttl4ma at v dd = 3.3 volt output parameters for ttl8ma at v dd = 3.3 volt parameter min typ max unit test conditions v oh v dd - 0.5 v v dd =3.15; i oh = -2.0/-8.0 v ol 0.4 v v dd = 3.15; i ol = 2.0/8.0 i ol 2.0/8.0 ma i oh -2.0/-8.0 ma t rise 10 ns c load = 15 pf t fall 10 ns c load = 15 pf leakage tri-state 10 a 0 to 3.45 v input parameter min typ max unit test conditions v oh 2.4 v dd vv dd = 3.15; i oh = -2.0 v ol 0.4 v v dd = 3.15; i ol = 4.0 i ol 4.0 ma i oh -2.0 ma t rise 8nsc load = 15 pf t fall 5nsc load = 15 pf parameter min typ max unit test conditions v oh 2.4 v dd vv dd = 3.15; i oh = -4.0 v ol 0.4 v v dd = 3.15; i ol = 8.0 i ol 8.0 ma i oh -4.0 ma t rise 10 ns c load = 25 pf t fall 5nsc load = 25 pf -31 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet input/output parameters for 3.3 volt operation input/output parameters for cmos2ma at v dd = 3.3 volt input/output parameters for ttl8ma (slew rate controlled) at v dd = 3.3 volt parameter min typ max unit test conditions v ih 2.2 v dd + 0.5 v 3.15 < v dd < 3.45 v il 1.0 v 3.15 < v dd < 3.45 input leakage current 10 av dd = 3.45 input capacitance 7.0 pf v oh v dd - 0.5 v v dd = 3.15; i oh = -2.0 v ol 0.4 v v dd = 3.15; i ol = 2.0 i ol 2.0 ma i oh -2.0 ma t rise 10 ns c load = 15 pf t fall 10 ns c load = 15 pf leakage tri-state 10 a 0 to 3.45 v input parameter min typ max unit test conditions v ih 2.0 v dd + 0.5 v 3.15 < v dd < 3.45 v il 0.8 v 3.15 < v dd < 3.45 input leakage current 10 av dd = 3.45 input capacitance 7.0 pf v oh 2.4 v dd vv dd = 3.15; i oh = -4.0 v ol 0.4 v v dd = 3.15; i ol = 8.0 i ol 8.0 ma i oh -4.0 ma t rise 10 ns c load = 25 pf t fall 5nsc load = 25 pf -32 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet timing characteristics detailed timing diagrams for the qe1f- plus are illustrated in figures 3 through 34, with values of the timing intervals tabulated below the waveform diagrams in each figure. all output times are measured with a maxi- mum 25 pf load capacitance, unless otherwise indicated. timing parameters are measured at voltage levels of (v ih +v il )/2 for input signals or (v oh +v ol )/2 for output signals, unless otherwise indicated. figure 3. dual unipolar (rail) receive interface timing notes: 1. lrclkn is shown for control bit rxcp (bit 6) in register x01h set to 0. data (rposn/rnegn) is clocked in on the rising edges of lrclkn when control bit rxcp is a 1. 2. the minimum frequency of sysclk must guarantee at least 9 rising edges of sysclk to occur between any two consecutive rising or falling edges of any particular lrclkn. parameter symbol min typ max unit lrclkn clock period t cyc 435 488.3 ns lrclkn high time t pwh 180 0.5 x t cyc ns lrclkn low time t pwl 180 0.5 x t cyc ns rposn/rnegn setup time to lrclkn t su 10 ns rposn/rnegn hold time after lrclkn t h 10 ns t su lrclkn rposn (input) rnegn (input) note: n=1, 2, 3, 4 t h t pwh t pwl t cyc -33 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet figure 4. dual unipolar (rail) transmit interface timing note: ltclkn is shown for control bit txcp (bit 7) in register x01h set to 1. data is clocked out on falling edges of ltclkn when control bit txcp is a 0. if transmit clock selection chooses recovered receive line clock (pin lrclkn) by set- ting control bits txc1 to a 1 and txc0 to a 0, the clock period and duty cycle will be the same as that received at lrclkn (pins 65, 74, 83 and 93). if the transmit clock selection is local oscillator lo (pin 41) or transmit clock tclkn (pins 33, 23, 13 and 4), the clock period and duty cycle will be the same as that received at the selected clock input pin. parameter symbol min typ max unit ltclkn clock period t cyc 488.3 ns ltclkn duty cycle (t pwh /t cyc )-- 50 % tposn/tnegn delay after ltclkn t d 0.0 5.0 20 ns t d ltclkn tposn t cyc (output) tnegn (output) note: n=1, 2, 3, 4 t pwh -34 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet figure 5. nrz receive interface timing (external transceiver) notes: 1. lrclkn is shown for control bit rxcp (bit 6 in register x01h) set to 0. rldatn and rlbpvn are clocked in on rising edges of lrclkn when control bit rxcp is a 1. the qe1f- plus accepts an inverted rldatn signal when control bit rxnrzp (bit 0 in register x01h) is a 1. control bit rxfs (bit 1 in register x06h) must be set to 0 to use the rlbpvn input. 2. the minimum frequency of sysclk must guarantee at least 9 rising edges of sysclk to occur between any two consecutive rising or falling edges of any particular lrclkn. parameter symbol min typ max unit lrclkn clock period t cyc 435 488.3 ns lrclkn high time t pwh 180 0.5 x t cyc ns lrclkn low time t pwl 180 0.5 x t cyc ns rldatn/rlbpvn setup time to lrclkn t su 10 ns rldatn/rlbpvn hold time after lrclkn t h 10 ns t pwh lrclkn t cyc t pwl (input) t su t h rldatn (input) t su t h rlbpvn (input) note: n=1, 2, 3, 4 external bipolar violation -35 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet figure 6. nrz transmit interface timing (external transceiver) note: ltclkn is shown for control bit txcp (bit 7 in register x01h) set to 1. tldatn and tmoden are clocked out on fall- ing edges of ltclkn when control bit txcp is a 0. the qe1f- plus provides an inverted tldatn signal when control bit txnrzp (bit 5 in register x06h) is a 1. control bit txfs (bit 0 in register x06h) must be set to 0 to obtain the tmoden output. if transmit clock selection chooses recovered receive line clock (pin lrclkn) by setting control bits txc1 to a 1 and txc0 to a 0, the clock period and duty cycle will be the same as that received at lrclkn (pins 65, 74, 83 and 93). if the transmit clock selection is local oscillator lo (pin 41) or transmit clock tclkn (pins 33, 23, 13 and 4), the clock period and duty cycle will be the same as that received at the selected clock input pin. parameter symbol min typ max unit ltclkn clock period t cyc 488.3 ns ltclkn duty cycle (t pwh /t cyc )-- 50 % tldatn/tmoden delay after ltclkn t d 0.0 5.0 20 ns t d ltclkn t cyc (output) tldatn (output) t d tmoden (output) note: n=1, 2, 3, 4 state determined by control bit be (bit 6 in x00h) t pwh -36 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet figure 7. nrz receive interface timing (fast sync mode) note: lrclkn is shown for control bit rxcp (bit 6 in register x01h) set to 0. data is clocked in on rising edges when con- trol bit rxcp is a 1. the qe1f- plus will accept an inverted rldatn signal when a 1 is written to control bit rxnrzp (bit 0 in register x01h). the fast sync mode is selected by writing a 1 to control bit rxfs (bit 1 in register x06h). parameter symbol min typ max unit lrclkn clock period t cyc(1) 435 488.3 ns lrclkn high time t pwh(1) 180 0.5 x t cyc(1) ns lrclkn low time t pwl(1) 180 0.5 x t cyc(1) ns rldatn/rfsn setup time to lrclkn t su 10 ns rldatn/rfsn hold time after lrclkn t h 10 ns rfsn period t cyc(2) 256 x 16 x t cyc(1) ns rfsn pulse width high time t pw 0.5 x t cyc(1) 1 x t cyc(1) 1.5 x t cyc(1) ns rldatn lrclkn (input) (input) t pwl(1) t pwh(1) t cyc(1) rfsn (input) t su t h bit 256 bit 1 bit 256 bit 1 t cyc(2) t h t su note: n=1, 2, 3, 4 t pw -37 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet figure 8. nrz transmit interface timing (fast sync mode) note: ltclkn is shown for control bit txcp (bit 7 in register x01h) set to 1. tldatn/tfsn are clocked out on falling edges of ltclkn when control bit txcp is a 0. the qe1f- plus will output an inverted tldatn signal when control bit txn- rzp (bit 5 in register x06h) is a 1. the fast sync mode is selected by writing a 1 to control bit txfs (bit 0 in register x06h). if transmit clock selection chooses recovered receive line clock (pin lrclkn) by setting control bits txc1 to a 1 and txc0 to a 0, the clock period and duty cycle will be the same as that received at lrclkn (pins 65, 74, 83 and 93). if the transmit clock selection is local oscillator lo (pin 41) or transmit clock tclkn (pins 33, 23, 13 and 4), the clock period and duty cycle will be the same as that received at the selected clock input pin. parameter symbol min typ max unit ltclkn clock period t cyc(1) 488.3 ns ltclkn duty cycle t pwh(1) /t cyc(1) 50 % tldatn/tfsn delay after ltclkn t d 0.0 5.0 20 ns tfsn pulse width high time t pw 1 x t cyc(1) ns tfsn period t cyc(2) 256 x 16 x t cyc(1) ns tldatn ltclkn (output) (output) t cyc(1) tfsn (output) bit 256 bit 1 bit 256 t d t pw t d t cyc(2) frame f+1 frame f note: n=1, 2, 3, 4 t pwh(1) -38 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet figure 9. serial port write timing notes: 1. the serial port interface for the line interface transceiver is selected when an active low is placed on the config2 pin (pin 42). 2. the clock period for lsclk is the same as provided on the lo pin (pin 41) since lsclk is derived from the signal at lo. parameter symbol min typ max unit lcsn pulse width high time t pw 300 ns lsclk clock period (note 2) t cyc 480 488.3 ns lsclk high time t pwh 190 0.5 x t cyc ns lsclk low time t pwl 190 0.5 x t cyc ns lcsn delay after lsclk t d(1) 10 15 20 ns lcsn delay after lsclk t d(2) 10 15 20 ns lsdo delay after lsclk t d(3) 15 25 50 ns t d(3) t cyc t pwh lsclk t pwl lcsn lsdo (output) (output) (output) t d(1) lsb lsb msb address/command data byte byte note: n=1, 2, 3, 4 t pw t d(2) -39 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet figure 10. serial port read timing notes: 1. the serial port interface for the line interface transceiver is selected when an active low is placed on the config2 pin (pin 42). 2. the clock period for lsclk is the same as provided on the lo pin (pin 41) since lsclk is derived from the signal at lo. parameter symbol min typ max unit lsdi setup time to lsclk t su 10 15 ns lsdi hold time after lsclk t h 10 15 ns lcsn delay after lsclk t d(1) 5.0 10 15 ns l csn delay after lsclk t d(2) 5.0 10 15 ns t d(2) lsclk lcsn lsdi (output) (output) (input) t d(1) t su t h -40 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet figure 11. monitor mode timing note: the monitor port is enabled when an active high is placed on the config2 pin (pin 42). control bits e1chcs1 and e1chcs0 (bits 1, 0 in register 013h) select the channel to be monitored. control bit rxtx (bit 3 in register 013h) selects either the receive side or transmit side to be monitored. writing a 0 to control bit esp/emon (bit 4 in register 013h) tri-states both outputs. the clock period and duty cycle depend on the particular signal being monitored. parameter symbol min typ max unit monclk clock period t cyc 488.3 ns monclk high time t pwh 0.5 x t cyc ns monclk low time t pwl 0.5 x t cyc ns mondto delay after monclk t d 70 75 90 ns mondto monclk (output) (output) t d t pwl t pwh t cyc -41 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet figure 12. receive highway timing - 2 mbit/s transmission mode (recovered receive line clock) note: the 2 mbit/s transmission mode is selected when a low is placed on the config1 pin (pin 43) and control bits hmvip and mtp16m (bits 2 and 1 in register 006h) are 00. the recovered receive line clock (rclkn) and an inter- nal sync pulse are used to clock out data (rdatan), signaling (rsigln), and the sync pulse (rsyncn) to the sys- tem, when control bits rxc and rse (bits 5 and 3 in register x02h) are 10 or 11. control bit rxc selects the clock source, while rse enables/disables the receive slip buffer. parameter symbol min typ max unit rclkn clock period t cyc 435 488.3 ns rclkn low time t pwl 180 0.5 x t cyc ns rclkn high time t pwh 180 0.5 x t cyc ns rdatan/rsigln delay after rclkn t d(1) 10 15 20 ns rsyncn delay after rclkn t d(2) 10 15 20 ns rsyncn pulse width t pw 435 488.3 ns rclkn rdatan rsigln t d(1) t cyc rsyncn bit 255 bit 256 t pwl bit 1 (first bit of time slot 0) (output) (outputs) (output) t pwh t pw t d(2) note: n=1, 2, 3, 4 -42 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet figure 13. receive highway timing - 2 mbit/s transmission mode (system clock) note: the 2 mbit/s transmission mode is selected when a low is placed on the config1 pin (pin 43) and control bits hmvip and mtp16m (bits 2 and 1 in register 006h) are 00. the system clock (rclkn) and sync pulse (rsyncn) are used to clock data out of the slip buffer when control bits rxc and rse (bits 5 and 3 in register x02h) are 01. control bit rxc selects the clock source, while rse enables/disables the receive slip buffer. the position of rsyncn with respect to the rdatan/rsigln signals can be offset. parameter symbol min typ max unit rclkn clock period t cyc 465 488.3 ns rclkn low time t pwl 233 0.5 x t cyc ns rclkn high time t pwh 233 0.5 x t cyc ns rdatan/rsigln delay after rclkn t d 20 25 35 ns rsyncn setup time to rclkn t su 5.0 ns rsyncn hold time after rclkn t h 5.0 ns rclkn rdatan rsigln t cyc rsyncn t pwl (input) (outputs) (input) t pwh note: n=1, 2, 3, 4 t su t h t d bit 255 bit 256 bit 1 (first bit of time slot 0) -43 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet figure 14. receive highway timing - 8 mbit/s transmission mode notes: 1. the 8 mbit/s transmission mode is selected when a low is placed on the config1 pin (pin 43) and control bits hmvip and mtp16m (bits 2 and 1 in register 006h) are 10. the receive slip buffer must be enabled for this mode. the position of rsync1 may be offset with respect to the rdata1 and rsigl1 signals. the value written to register 018h compensates for any offset. rsync1 is shown for an offset equal to zero. 2. rsync1 pulse width may be wider than two rclk1 clock periods as long as only two rising edges of rclk1 occur during the rsync1 pulse. parameter symbol min typ max unit rclk1 clock period t cyc 58 61 ns rclk1 low time t pwl 28 0.5 x t cyc ns rclk1 high time t pwh 28 0.5 x t cyc ns rdata1/rsigl1 delay after rclk1 t d 20 25 35 ns rsync1 setup time to rclk1 t su 5.0 ns rsync1 hold time after rclk1 t h 5.0 ns rsync1 pulse width high time (note 2) t pw 2 x t cyc 2 x t cyc <3 x t cyc ns rsync1 (input) t d t h t su rclk1 (input) rdata1 rsigl1 framer no. 4 time slot 31 bit 8 framer no. 1 time slot 0 bit 1 note: see note 1 below. all frame time slots are byte-interleaved on data and signaling highways. (outputs) t pw t cyc t pwl t pwh -44 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet figure 15. transmit highway timing - 8 mbit/s transmission mode notes: 1. the 8 mbit/s transmission mode is selected when a low is placed on the config1 pin (pin 43) and control bits hmvip and mtp16m (bits 2 and 1 in register 006h) are 10. the position of tsync1 may be offset with respect to the tdata1 signal. the value written to register 017h compensates for any offset. tsync1 is shown for an offset equal to zero. 2. tsync1 pulse width may be wider than two tclk1 clock periods as long as only two rising edges of tclk1 occur during the tsync1 pulse. parameter symbol min typ max unit tclk1 clock period t cyc 58 61 ns tclk1 low time t pwl 28 0.5 x t cyc ns tclk1 high time t pwh 28 0.5 x t cyc ns tdata1/tsigl1 setup time to tclk1 t su(1) 5.0 ns tdata1/tsigl1 hold time after tclk1 t h(1) 5.0 ns tsync1 setup time to tclk1 t su(2) 5.0 ns tsync1 hold time after tclk1 t h(2) 5.0 ns tsync1 pulse width (note 2) t pw 2 x t cyc 2 x t cyc < 3 x t cyc ns tsync1 (input) t su(2) t h(2) tclk1 (input) tdata1 tsigl1 framer no. 4 time slot 31 bit 8 t pw t su(1) t h(1) (inputs) t pwl t pwh t cyc see note 1 below. -45 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet figure 16. receive highway timing - 16 mbit/s transmission mode notes: 1. the 16 mbit/s transmission mode is selected when a low is placed on the config1 pin (pin 43) and control bits hmvip and mtp16m (bits 2 and 1 in register 006h) are 01. the receive slip buffer must be enabled for this mode. the position of rsync1 may be offset with respect to the rdata1 signal. the value written to register 018h com- pensates for any offset. rsync1 is shown for an offset equal to zero. 2. rsync1 pulse width may be wider than one rclk1 clock period as long as only a single rising edge of rclk1 occurs during the rsync1 pulse. parameter symbol min typ max unit rclk1 clock period t cyc 58 61 ns rclk1 low time t pwl 28 0.5 x t cyc ns rclk1 high time t pwh 28 0.5 x t cyc ns rdata1 delay after rclk1 t d 20 25 35 ns rsync1 setup time to rclk1 t su 5.0 ns rsync1 hold time after rclk1 t h 5.0 ns rsync1 pulse width high time (note 2) t pw 1 x t cyc 1 x t cyc < 2 x t cyc ns rdata1 rclk1 (input) (output) t pw rsync1 (input) framer no. 1 data ts0 bit 1 framer no. 4 signaling ts31 bit 8 framer no. 1 signaling ts0 bit 1 t su t d t cyc t pwl t pwh 2 ms note: see note 1 below. all four framers ? data and signaling time slots are bit-interleaved. a multiframe is multiframe m multiframe m+1 t h 16 frames long (2 ms). -46 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet figure 17. transmit highway timing - 16 mbit/s transmission mode notes: 1. the 16 mbit/s transmission mode is selected when a low is placed on the config1 pin (pin 43) and control bits hmvip and mtp16m (bits 2 and 1 in register 006h) are 01. the position of tsync1 may be offset with respect to the tdata1 signal. the value written to register 017h compensates for any offset. tsync1 is shown for an offset equal to zero. 2. tsync1 pulse width may be wider than one tclk1 clock period as long as only a single rising edge of tclk1 occurs during the tsync1 pulse. parameter symbol min typ max unit tclk1 clock period t cyc 58 61 70 ns tclk1 low time t pwl 28 0.5 x t cyc 35 ns tclk1 high time t pwh 28 0.5 x t cyc 35 ns tdata1 setup time to tclk1 t su(1) 5.0 ns tdata1 hold time after tclk1 t h(1) 5.0 ns tsync1 setup time to tclk1 t su(2) 5.0 ns tsync1 hold time after tclk1 t h(2) 5.0 ns tsync1 pulse width high time (note 2) t pw 1 x t cyc 1 x t cyc < 2 x t cyc ns tsync1 (input) tclk1 (input) tdata1 (input) t pw t su(1) t h(1) t h(2) t su(2) t cyc t pwl t pwh framer no. 1 data ts0 bit 1 framer no. 4 signaling ts31 bit 8 note: see note 1 below. all four framers ? data and signaling time slots are bit-interleaved. a multiframe is 16 frames long (2 ms). -47 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet figure 18. transmit highway timing - 2 mbit/s transmission mode note: the 2 mbit/s transmission mode is selected when a low is placed on the config1 pin (pin 43) and control bits hmvip and mtp16m (bits 2 and 1 in register 006h) are 00. the position of tsyncn may be offset with respect to the tdatan/tsigln signals. the value written to register 017h compensates for any offset. tsyncn is shown for an offset equal to zero. parameter symbol min typ max unit tclkn clock period t cyc 435 488.3 ns tclkn low time t pwl 180 0.5 x t cyc ns tclkn high time t pwh 180 0.5 x t cyc ns tdatan/tsigln setup time to tclkn t su(1) 5.0 ns tdatan/tsigln hold time after tclkn t h(1) 5.0 ns tsyncn setup time to tclkn t su(2) 5.0 ns tsyncn hold time after tclkn t h(2) 5.0 ns tclkn tdatan tsigln t cyc tsyncn bit 255 bit 256 t pwl bit 1 (first bit of time slot 0) (input) (inputs) (input) t pwh note: n=1, 2, 3, 4 t su(2) t h(2) t su(1) t h(1) -48 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet figure 19. receive highway timing - 2 mbit/s mvip mode notes: 1. the 2 mbit/s mvip mode is selected when a high is placed on the config1 pin (pin 43) and control bits hmvip and mtp16m (bits 2 and 1 in register 006h) are 00. the receive slip buffer is always enabled in this mode. the position of rsyncn may be offset with respect to the rdatan/rsigln signals. the value written to register 018h compen- sates for any offset. rsyncn is shown for an offset equal to zero. 2. for bit number per mvip bit identification nomenclature, bit 256 is bit 0 of time slot 31, bit 1 is bit 7 of time slot 0 and bit 2 is bit 6 of time slot 0. 3. rsyncn pulse width may be wider than one rclkn clock period as long as only a single rising edge of rclkn occurs during the rsyncn pulse. parameter symbol min typ max unit rclkn clock period t cyc 465 488.3 ns rclkn low time t pwl 233 0.5 x t cyc ns rclkn high time t pwh 233 0.5 x t cyc ns rdatan/rsigln delay after rclkn t d 25 35 50 ns rsyncn setup time to rclkn t su 0.0 ns rsyncn hold time after rclkn t h 10 ns rsyncn pulse width low time (note 3) t pw 1 x t cyc 1 x t cyc < 2 x t cyc ns rclkn rdatan rsigln t cyc rsyncn bit 256 bit 1 (first bit of time slot 0) t pwh t d t pwl t h t su t pw (input) (outputs) (input) note: see note 1 below. n=1, 2, 3, 4 bit 2 (second bit of time slot 0) (see note 2) -49 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet figure 20. transmit highway timing - 2 mbit/s mvip mode notes: 1. the 2 mbit/s mvip mode is selected when a high is placed on the config1 pin (pin 43) and control bits hmvip and mtp16m (bits 2 and 1 in register 006h) are 00. the transmit slip buffer is always enabled in this mode. the position of tsyncn may be offset with respect to the tdatan/tsigln signals. the value written to register 017h compen- sates for any offset. tsyncn is shown for an offset equal to zero. 2. for bit number per mvip bit identification nomenclature, bit 256 is bit 0 of time slot 31, bit 1 is bit 7 of time slot 0 and bit 2 is bit 6 of time slot 0. 3. tsyncn pulse width may be wider than one tclkn clock period as long as only a single rising edge of tclkn occurs during the tsyncn pulse. parameter symbol min typ max unit tclkn clock period t cyc 465 488.3 ns tclkn low time t pwl 233 0.5 x t cyc ns tclkn high time t pwh 233 0.5 x t cyc ns tdatan/tsigln setup time to tclkn t su(1) 0.0 ns tdatan/tsigln hold time after tclkn t h(1) 5.0 ns tsyncn setup time to tclkn t su(2) 15 ns tsyncn hold time after tclkn t h(2) 15 ns tsyncn pulse width low time (note 3) t pw 1 x t cyc 1 x t cyc < 2 x t cyc ns tclkn tdatan tsigln t cyc tsyncn bit 256 bit 1 (first bit of time slot 0) t pwh t pwl t h(2) t su(2) t pw (input) (inputs) (input) note: see note 1 below. n=1, 2, 3, 4 t su(1) t h(1) bit 2 (second bit of time slot 0) (see note 2) -50 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet figure 21. receive highway timing - 8 mbit/s h-mvip/ h.100 mode notes: 1. the 8 mbit/s h-mvip/h.100 mode is selected when a high is placed on the config1 pin (pin 43) and control bits hmvip and mtp16m (bits 2 and 1 in register 006h) are 10. the receive slip buffer must be enabled for this mode. the position of rsync1 may be offset with respect to the rdata1 and rsigl1 signals. the value written to register 018h compensates for any offset. rsync1 is shown for an offset equal to zero. control bit h100 (bit 2 of register 0ffh) controls the pulse width criteria of rsync1 required by the qe1f- plus . 2. rsync1 pulse width may be wider than 4 or 2 clock periods as long as only either 4 or 2 rising edges of rclk1 occur during the rsync1 pulse (for h-mvip and h.100, respectively). 3. in mvip nomenclature, time slot 31 bit 8 is known as time slot 31 bit 0 and time slot 0 bit 1 is time slot 0 bit 7. parameter symbol min typ max unit rclk1 clock period t cyc 60 61 ns rclk1 low time t pwl 30 0.5 x t cyc ns rclk1 high time t pwh 30 0.5 x t cyc ns rdata1/rsigl1 delay after rclk1 t d 10 15 20 ns rsync1 setup time to rclk1 ; h-mvip t su(1) 9.0 ns rsync1 hold time after rclk1 ; h-mvip t h(1) 5.0 ns rsync1 setup time to rclk1 ; h.100 t su(2) 9.0 ns rsync1 hold time after rclk1 ; h.100 t h(2) 5.0 ns rsync1 pulse width low time; h-mvip (note 2) t pw(1) 4 x t cyc 4 x t cyc < 5 x t cyc ns rsync1 pulse width low time; h.100 (note 2) t pw(2) 2 x t cyc 2 x t cyc < 3 x t cyc ns rsync1 (input: control bit h100 = 0) t d t h(1) t su(1) rclk1 (input) rdata1 rsigl1 framer no. 4 time slot 31 bit 8 framer no. 1 time slot 0 bit 1 note: see note 1 below. all four framers ? time slots are byte-interleaved. t pw(1) (outputs) t cyc t pwh t pwl frame f + 1 frame f rsync1 (input: control bit h100 = 1) t h(2) t su(2) t pw(2) (see note 3) -51 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet figure 22. transmit highway timing - 8 mbit/s h-mvip/h.100 mode notes: 1. the 8 mbit/s h-mvip/h.100 mode is selected when a high is placed on the config1 pin (pin 43) and control bits hmvip and mtp16m (bits 2 and 1 in register 006h) are 10. the position of tsync1 may be offset with respect to the tdata1 signal. the value written to register 017h compensates for any offset. tsync1 is shown for an offset equal to zero. 2. tsync1 pulse width may be wider than 4 or 2 tclk1 clock periods as long as only either 4 or 2 rising edges of tclk1 occur during the tsync1 pulse (for h-mvip or h.100, respectively). 3. in mvip nomenclature, time slot 31 bit 8 is known as time slot 31 bit 0 and time slot 0 bit 1 is time slot 0 bit 7. parameter symbol min typ max unit tclk1 clock period t cyc 60 61 ns tclk1 low time t pwl 30 0.5 x t cyc ns tclk1 high time t pwh 30 0.5 x t cyc ns tdata1/tsigl1 setup time to tclk1 t su(1) 7.0 ns tdata1/tsigl1 hold time after tclk1 t h(1) 2.0 ns tsync1 setup time to tclk1 ; h-mvip t su(2) 10 ns tsync1 hold time after tclk1 ; h-mvip t h(2) 5.0 ns tsync1 setup time to tclk1 ; h.100 t su(3) 10 ns tsync1 hold time after tclk1 ; h.100 t h(3) 5.0 ns tsync1 pulse width low time; h-mvip (note 2) t pw(1) 4 x t cyc 4 x t cyc < 5 x t cyc ns tsync1 pulse width low time; h.100 (note 2) t pw(2) 2 x t cyc 2 x t cyc < 3 x t cyc ns tdata1 tclk1 (input) tsigl1 tsync1 (input: control bit note: see note 1 below. all four framers ? time slots are byte-interleaved. (inputs) t cyc t pwl t pwh frame f + 1 frame f t h(2) t su(2) t pw(1) t h(1) t su(1) framer no. 1 time slot 0 bit 1 h100 = 0) tsync1 (input: control bit h100 = 1) t h(3) t su(3) t pw(2) (see note 3) -52 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet figure 23. receive highway timing - 16 mbit/s pcm highway mode notes: 1. the 16 mbit/s pcm highway mode is selected when a high is placed on the config1 pin (pin 43) and control bits hmvip and mtp16m (bits 2 and 1 in register 006h) are 01. the receive slip buffer must be enabled for this mode. the position of rsync1 may be offset with respect to the rdata1 signal. the value written to register 018h com- pensates for any offset. rsync1 is shown for an offset equal to zero. 2. rsync1 pulse width may be wider than one rclk1 clock period as long as only a single rising edge of rclk1 occurs during the rsync1 pulse. parameter symbol min typ max unit rclk1 clock period t cyc 60 61 ns rclk1 low time t pwl 30 0.5 x t cyc ns rclk1 high time t pwh 30 0.5 x t cyc ns rdata1 delay after rclk1 t d 15 25 30 ns rsync1 setup time to rclk1 t su 6.0 ns rsync1 hold time after rclk1 t h 0.0 ns rsync1 pulse width high time (note 2) t pw 1 x t cyc 1 x t cyc < 2 x t cyc ns rdata1 rclk1 (input) (output) t pw rsync1 (input) framer no. 1 data ts0 bit 1 framer no. 4 signaling ts31 bit 8 framer no. 1 signaling ts0 bit 1 t su t h t d t cyc t pwl t pwh 125 s note: see note 1 below. all four framers ? data and signaling time slots are bit-interleaved. frame f frame f + 1 -53 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet figure 24. transmit highway timing - 16 mbit/s pcm highway mode notes: 1. the 16 mbit/s pcm highway mode is selected when a high is placed on the config1 pin (pin 43) and control bits hmvip and mtp16m (bits 2 and 1 in register 006h) are 01. the transmit slip buffer must be enabled for this mode. the position of tsync1 may be offset with respect to the tdata1 signal. the value written to register 017h com- pensates for any offset. tsync1 is shown for an offset equal to zero. 2. tsync1 pulse width may be wider than one tclk1 clock period as long as only a single rising edge of tclk1 occurs during the tsync1 pulse. parameter symbol min typ max unit tclk1 clock period t cyc 60 61 ns tclk1 low time t pwl 30 0.5 x t cyc ns tclk1 high time t pwh 30 0.5 x t cyc ns tdata1 setup time to tclk1 t su(1) 5.0 ns tdata1 hold time after tclk1 t h(1) 0.0 ns tsync1 setup time to tclk1 t su(2) 2.0 ns tsync1 hold time after tclk1 t h(2) 0.0 ns tsync1 pulse width high time (note 2) t pw 1 x t cyc 1 x t cyc < 2 x t cyc ns tsync1 (input) t pw tclk1 (input) tdata1 framer no. 1 data time slot 0 t su(1) t h(1) (input) bit 1 t su(2) t h(2) framer no. 4 signaling time slot 31 bit 8 note: see note 1 below. all four framers ? data and signaling time slots are bit-interleaved. t cyc t pwl t pwh -54 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet figure 25. receive highway timing - fractional e1 gapped clock (transmission mode; receive line clock) note: the fractional e1 gapped clock feature is enabled when the config1 pin is low, control bit fe1m (bit 0 in register x02h) is written with a 1 and control bits hmvip and mtp16m are both set to 0 (bits 2 and 1 of register 006h). one or more time slots may be selected by writing a 1 to one or more control bits rfts0-rfts31 (in registers x38h-x3bh). parameter symbol min typ max unit rclkn clock period t cyc 435 488.3 ns rclkn low time t pwl 180 0.5 x t cyc ns rclkn high time t pwh 180 0.5 x t cyc ns rdatan delay after rclkn t d(1) 10 15 23 ns rfe1gcn delay after rclkn t d(2) 10 15 20 ns rsyncn delay after rclkn t d(3) 10 15 20 ns rsyncn pulse width t pw 435 488.3 ns rclkn (output) rdatan (output) rfe1gcn (output) rsyncn (output) 12345678910 t d(3) t pw t d(2) t pwl t pwh t cyc t d(1) ch1 when selected 256 note: n = 1, 2, 3, 4 -55 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet figure 26. receive highway timing - fractional e1 gapped clock (transmission and 2 mbit/s mvipmodes; system clock) note: the fractional e1 gapped clock feature is enabled when the config1 pin is low (transmission modes), or high (mvip modes), control bit fe1m (bit 0 in register x02h) is written with a 1, and control bits hmvip and mtp16m are both set to 0 (bits 2 and 1 of register 006h). one or more time slots may be selected by writing a 1 to one or more control bits rfts0-rfts31 (in registers x38h-x3bh). parameter symbol min typ max unit rclkn clock period t cyc 465 488.3 ns rclkn low time t pwl 180 0.5 x t cyc ns rclkn high time t pwh 180 0.5 x t cyc ns rdatan delay after rclkn t d(1) 20 25 30 ns rfe1gcn delay after rclkn t d(2) 20 25 30 ns rsyncn setup time to rclkn (transmission) t su(1) 5.0 ns rsyncn hold time after rclkn (transmission) t h(1) 5.0 ns rsyncn setup time to rclkn (mvip) t su(2) 0.0 ns rsyncn hold time after rclkn (mvip) t h(2) 10 ns rclkn (input) rdatan (output) rfe1gcn (output) rsyncn (input) 12345678910 t su(1) t h(1) t d(2) t pwl t pwh t cyc t d(1) ch1 when selected 256 transmission mode or rsyncn (input) t su(2) t h(2) note: n = 1, 2, 3, 4 2 mbit/s mvip mode -56 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet figure 27. transmit highway timing - fractional e1 gapped clock (transmission and 2 mbit/s mvip modes) (cont. on next page) parameter symbol min typ max unit tclkn clock period t cyc 435 488.3 ns tclkn low time t pwl 180 0.5 x t cyc ns tclkn high time t pwh 180 0.5 x t cyc ns tdatan setup time to tclkn t su(1) 5.0 ns tdatan hold time after tclkn t h(1) 5.0 ns tsyncn setup time to tclkn t su(2) 5.0 ns tsyncn hold time after tclkn t h(2) 5.0 ns tfe1gcn output delay from tclkn t d 5.0 10 27 ns 12345678910 t pwl t pwh t cyc t su(1) for the time slot selected t d tclkn (input) tfe1gcn (output) tsyncn (input) t h(1) t h(2) t su(2) 256 transmission mode note: the fractional e1 gapped clock feature is enabled when the config1 pin is low (transmission modes), or high (mvip modes), control bit fe1m (bit 0 in register x02h) is written with a 1, and control bits hmvip and mtp16m (bits 2 and 1 in control register 006h) are both written with a 0. one or more time slots may be selected by writing a 1 to one or more control bits tfts0-tfts31 (in registers x3ch-x3fh). n = 1,2,3,4. tdatan (input) 12345678910 t pwh t pwl t cyc t su(1) for the time slot selected t d tclkn (input) tfe1gcn (output) tsyncn (input) t h(1) t h(2) t su(2) 256 2 mbit/s mvip mode t pw tdatan (inputs, tsigln see note 2) -57 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet figure 27. (cont.) notes: 1. see figure 20 for additional detail. 2. for bit number per mvip bit identification nomenclature, bit 256 is bit 0 of time slot 31, bit 1 is bit 7 of time slot 0 and bit 2 is bit 6 of time slot 0. 3. tsyncn pulse width may be wider than one tclkn clock period as long as only a single rising edge of tclkn occurs during the tsyncn pulse. figure 28. shadow register timing notes: 1. a duty cycle (t pwh /t cyc ) of 50% for the t1si signal is permitted. 2. the shadow register feature and this input are enabled when a 1 is written to control bit enpmfm (bit 3 in register 006h). parameter symbol min typ max unit tclkn clock period t cyc 465 488.3 ns tclkn low time t pwl 233 0.5 x t cyc ns tclkn high time t pwh 233 0.5 x t cyc ns tdatan/tsigln setup time to tclkn t su(1) 0.0 ns tdatan/tsigln hold time after tclkn t h(1) 5.0 ns tfe1gcn output delay from tclkn t d 5.0 10 27 ns tsyncn setup time to tclkn t su(2) 15 ns tsyncn hold time after tclkn t h(2) 15 ns tsyncn pulse width low time (note 3) t pw 1 x t cyc 1 x t cyc < 2 x t cyc ns parameter symbol min typ max unit t1si cycle time t cyc 1000 ms t1si pulse width high (note 1) t pwh 20 50 ms t1si pulse width low t pwl 950 980 ms t1si (input) t pwl t cyc t pwh -58 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet figure 29. boundary scan timing parameter symbol min max unit tck clock high time t pwh 50 ns tck clock low time t pwl 50 ns tms setup time to tck t su(1) 5.0 ns tms hold time after tck t h(1) 5.0 ns tdi setup time to tck t su(2) 5.0 ns tdi hold time after tck t h(2) 10 ns tdo delay from tck t d 6.5 13 ns tms tdi tdo t d tck (input) (input) (input) (output) t h(2) t su(2) t su(1) t h(1) t pwh t pwl -59 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet figure 30. intel microprocessor read cycle timing notes: 1. the intel microprocessor bus is selected by placing a low on the moto pin (pin 99). 2. the system clock has a nominal frequency of 19-22 mhz. 3. both sel and rd must be simultaneously low for the specified t pw(1) interval. parameter symbol min typ max unit addr valid setup time to sel t su(1) 10 ns addr hold after sel t h(1) 0.0 ns dat valid delay after rdy t d(1) -1/2 cycle of sysclk -10 ns dat float time after rd t f 5.0 10 15 ns sel hold time after rd t h(2) 10 ns rd pulse width low time (note 3) t pw(1) 25 ns rdy delay after rd t d(2) 5.0 20 25 ns rdy pulse width low time t pw(2) 2 cycles of sysclk 10 cycles of sysclk 15 cycles of sysclk ns rdy tri-state to high delay after the latter of sel or rd t d(3) 5.0 25 ns rdy high to tri-state delay after sel t d(4) 17 ns addr(11-0) dat(7-0) sel rd rdy t h(2) t f t d(1) t pw(2) t d(2) t su(1) t pw(1) (input) (output) (input) (input) (output) tri-state tri-state t d(4) t d(3) t h(1) -60 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet figure 31. intel microprocessor write cycle timing (cont. on next page) parameter symbol min typ max unit addr valid setup time to sel t su(1) 5.0 ns addr hold time after wr ,sel (note 4) t h(1) 10 ns dat valid setup time to wr , sel (note 4) t su(2) 10 ns dat hold time after wr , sel (note 4) t h(2) 10 ns sel hold time after wr (note 5) t h(3) 0.0 ns wr pulse width low time/sel pulse width low time (note 5) t pw(1) 50 ns rdy delay after wr t d(2) 15 20 25 ns rdy pulse width low time t pw(2) 0.0 7 cycles of sysclk* 10 cycles of sysclk* ns rdy tri-state to high delay after the latter of sel or wr t d(3) 5.0 25 ns rdy high to tri-state delay after sel t d(4) 17 20 25 ns rdy high setup time to wr ,sel (note 4) t su(4) 0.0 ns rdy to wr , or sel (note 6) t h(4) 2 cycles of sysclk ns addr(11-0) dat(7-0) sel wr rdy t h(2) t su(1) t pw(2) t d(2) t pw(1) t su(2) t h(1) (input) (input) (input) (input) (output) tri-state tri-state t d(4) t d(3) t su(4) t h(3) t h(4) -61 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet figure 31. (cont.) notes: 1. the intel microprocessor bus is selected by placing a low on the moto pin (pin 99). 2. the system clock has a nominal frequency of 19-22 mhz. 3. * wait states only occur if a write cycle immediately follows a previous read/write cycle (e.g., read, modify, write or word-wide write). 4. the timing is with respect to the earlier of the two rising edges. 5. as long as both sel and wr are simultaneously low for the specified t pw(1) interval, sel may rise prior to wr ( t h(3) is a negative min). 6. when writing to address x0ah (hdlc transmit fifo) only, allow a minimum of 2 cycles of sysclk between rdy and sel or wr . -62 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet figure 32. motorola microprocessor read cycle timing notes: 1. the motorola microprocessor bus is selected by placing a high on the moto pin (pin 99). 2. the system clock has a nominal frequency of 19-22 mhz. parameter symbol min typ max unit addr valid setup time to sel t su(1) 10 ns dat delay to tri-state after sel t d(3) 10 ns dat valid output delay after dtack t d(1) -1 cycle of sysclk -1/2 cycle of sysclk -10 ns sel pulse width low time t pw(1) 50 ns rd/w r setup time to sel t su(3) 10 ns dtack pulse width high time t pw(2) 2 cycles of sysclk 10 cycles of sysclk 15 cycles of sysclk ns dtack float time after sel t f 7.0 8.0 12 ns dtack delay after sel t d(2) 9.0 10 12 ns addr hold after sel t h(1) 0.0 ns rd/wr hold after sel t h(2) 5.0 ns addr(11-0) dat(7-0) sel rd/wr dtack t f t d(3) t d(1) t pw(2) t su(3) t su(1) t pw(1) t d(2) (input) (output) (input) (input) (output) tri-state tri-state t h(2) t h(1) -63 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet figure 33. motorola microprocessor write cycle timing notes: 1. the motorola microprocessor bus is selected by placing a high on the moto pin (pin 99). 2. the system clock has a nominal frequency of 19-22 mhz. 3. * wait states only occur if a write cycle immediately follows a previous read or write cycle (e.g., read, modify, write or word-wide write). 4. sel and rd/wr must both be low simultaneously for the specified t pw(1) period. 5. when writing to address x0ah (hdlc transmit fifo) only, allow a minimum of 2 cycles of sysclk between dtack and sel or rd/wr . parameter symbol min typ max unit addr valid setup time to sel t su(1) 10 ns addr hold time after sel t h(1) 10 ns dat valid setup time to sel t su(2) 15 ns sel pulse width low time (note 4) t pw(1) 50 ns dat hold time after sel t h(2) 10 ns rd/w r setup time to sel t su(3) 10 ns rd/wr hold time after sel t h(3) 10 ns dtack pulse width high time t pw(2) 0.0 10 cycles of sysclk* 15 cycles of sysclk* ns dtack float time after sel t f 7.0 7.0 10 ns dtack delay after sel t d(2) 10 12 15 ns dtack low setup time to sel t su(5) 0.0 ns dtack to sel or rd/ wr (note 5) t h(4) 2 cycles of sysclk ns addr(11-0) dat(7-0) sel rd/wr t f t pw(2) t su(1) t su(3) dtack t su(2) t h(2) t pw(1) t d(2) t h(1) (input) (input) (input) (input) (output) tri-state tri-state t h(3) t su(5) t h(4) -64 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet figure 34. clock reference timing notes: 1. clkref1 and clkref2 output pins are controlled by register 019h. control bit 2048khz selects either a direct clock output when set to 1 or via a divide by 256 circuit when set to 0. control bits enref1 and enref2 enable out- put pins clkref1 and clkref2 when set to 1; when enref1 and enref2 are set to 0 clkref1 and clkref2 are tri-stated. the particular receive clock lrclkn used as a reference is selected by control bits cr1s1,2 for clkref1 and control bits cr2s1,2 for clkref2. 2. the actual clock period and high or low times are a function of the selected clock lrclkn. 3. a fault detected (los or lint pin active if enabled by control bit lie) by the particular channel selected for the refer- ence clock will cause clkref1,2 to stay low. the output only goes to tri-state if control bit enref1 or enref2 is set to 0. parameter symbol min typ max unit clkref1,2 clock period when control bit 2048khz = 1; (note 2) t cyc(1) 488.3 ns clkref1,2 high time when control bit 2048khz = 1; (note 2) t pwh(1) 0.5 t cyc(1) ns clkref1,2 low time when control bit 2048khz = 1; (note 2) t pwl(1) 0.5 t cyc(1) ns clkref1,2 clock period when control bit 2048khz = 0; (note 2) t cyc(2) 125 s clkref1,2 high time when control bit 2048khz = 0; (note 2) t pwh(2) 1 t cyc(1) ns clkref2 (output) t pwl(1) t pwh(1) t cyc(1) clkref2 (output) t cyc(2) t pwh(2) (control bit 2048khz = 1) (control bit 2048khz = 0) clkref1 clkref1 note 3 note 3 -65 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet operation the following sections detail the internal operation of the qe1f- plus . line interface selection each of the four framers in the qe1f- plus can be programmed to provide either a dual unipolar interface or a nrz interface. the dual unipolar interface is selected when a 1 is written into control bit rail (bit 7) in the framer configuration register located at address x00h in the memory map. the x stands for the framer selected, and will be equal to the value n used to identify the framer (1 for framer 1, 2 for framer 2, etc.). the hdb3 line coder/decoder (codec) feature is usually selected for the dual unipolar interface. the hdb3 codec is selected by writing a 1 to control bit be (bit 6) in the framer configuration register x00h. a 0 will select an ami codec. the hdb3 stands for high density bipolar of order 3, which is described in itu-t rec- ommendation g.703. the clock polarity of the input and output line clocks is selectable by writing the sense required to control bits txcp and rxcp (bits 7 and 6) in the framer configuration register x01h. when a framer is configured for the dual unipolar mode, the line signal is monitored for loss of signal. the los detection and recovery periods for all four framers are programmable by writing the two consecutive pulse count values to the global configura- tion registers 01ah and 01bh. typical values are 255 for detection and 32 for recovery. the connections between a qe1f- plus framer and external line interface transceivers are shown in figure 35 below for dual unipolar mode. figure 35. line interface for dual unipolar mode line interface transceiver qe1f- plus receive rposn rnegn lrclkn tposn tnegn lt c l k n lc sn lintn lsclk lsdo lsdi cs los sclk sdi sdo rxtip rxring txtip txring transmit note: n is the channel number (1, 2, 3, 4) other transceivers for channel n -66 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet the nrz interface is selected when a 0 is written into control bit rail (bit 7) in register x00h. the clock polarity of the line input and output clocks is selectable by writing to control bits txcp and rxcp (bits 7 and 6) in the framer configuration register x01h. options are provided for inverting the polarity of the transmit and receive data pins. a 1 written to control bit txnrzp (bit 5) in register x01h inverts the polarity of the transmit data signal, tldatn, while a 1 written to control bit rxnrzp (bit 0) in the same register inverts the polarity of the receive data signal rldatn. in nrz mode, the rnegn pin may be used to input an external indication of coding violations (rlbpvn) or a fast sync pulse for testing purposes (rfsn). external coding violations are counted in a 16-bit performance counter when control bit rxfs (bit 1) in register x06h is a 0. coding violations are counted when the input is high for rising edges of the line clock lrclkn. when control bit rxfs is a 1, this pin is used for inputting a receive fast sync pulse. in the transmit direction, when the nrz mode is selected, the tnegn pin becomes a tfsn or tmoden pin. the pin may be used to output a fast sync pulse (tfsn), or it may be used as a general purpose output pin (tmoden). when control bit txfs (bit 0) in register x06h is a 1, a fast sync output pulse is provided on this pin. when control bit txfs is a 0, this pin can be used as a general purpose output pin. the output state is defined by the value written to bit be (bit 6) in register x00h. a typical interface between a framer in the qe1f- plus and an external line transceiver is shown in figure 36 below for nrz mode. figure 36. line interface for nrz mode qe1f- plus receive rldatn rlbpvn lrclkn tldatn tmoden lt c l k n lcsn lintn lsclk lsdo lsdi cs los sclk sdi sdo rxtip rxring txtip txring transmit note: n is the channel number (1, 2, 3, 4) other transceivers line interface transceiver for channel n -67 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet line interface control this interface permits the microprocessor to have complete control of the four external line interface transceiv- ers through the qe1f- plus . this interface is selected by placing a low on the config2 pin (pin 42). the line interface control leads are common to all four framers and comprise a data input pin (lsdi), a data output pin (lsdo), and a clock output pin (lsclk). the clock signal lsclk is derived from the signal at the lo pin (pin 41); it is the same frequency as the signal applied to the lo pin. individual chip select pins (lcsn ) are used between the qe1f- plus and the external transceivers to determine which of the four external transceivers is to be accessed through the qe1f- plus . in addition, general purpose input leads (lintn) are provided. the signal on this lead is locally or-gated with the internal loss of signal alarm when control bit lie (bit 1) in the framer configuration register x00h is a 1. the operating sense of this lead is programmable by control bit lpol (bit 0) in the framer configuration register x00h. the status indication of this pin is given by the lint status bit (bit 0) in register x15h. a typical interface between the qe1f- plus and external line interface transceivers using the line interface control pins is shown in figures 35 and 36, for the dual unipolar and nrz interface modes respectively. data to be written to the external transceiver is formatted as a two-byte message. the first byte is an address/ command byte and the second byte contains the data to be written. figure 37 illustrates the message and con- trol formats associated with the transceiver serial i/o timing. figure 37. transceiver serial i/o timing the format of the address/command byte depends upon the external transceiver being controlled. please refer to the transceiver's data sheet for the command/data formats. the interface for controlling the external trans- ceiver operates in the following way. the external transceiver selection (via lcsn ) is determined by the value written to two e1chcs bits (bits 1 and 0) in register 013h. for example, a 00 value selects the transceiver for framer 1 while a 11 value selects the transceiver for framer 4. the microprocessor writes the command byte to lcb7-lcb0 in the line interface control register 010h. this is followed by writing the data byte to ldo7- ldo0 in line interface control register 011h. the serial message is sent on lsdo when a 1 is written to replace the 0 in the esp/emon bit (bit 4) in register 013h. the esp/emon bit must be first written with a 0, followed by a 1, before another transfer can take place between the qe1f- plus and the external transceiver selected. broadcast capability to all transceivers is enabled when the control bit bdcst (bit 7) in register 013h is written with a 1. eight clock cycles later, the selected transceiver will respond by sending serial data on the lsdi input pin. the data is shifted in lsb first to ldi7-ldi0 in the serial port data input register 012h. monitor mode the monitor mode interface permits the qe1f- plus to provide an external receive or transmit nrz signal from one of the framers to an external device. this interface is selected by placing a high on the config2 pin (pin 42). please note that the pins for this mode are shared with the line control interface, and if the monitor mode is selected, these pins cannot be used to provide a serial interface between the external transceivers and the qe1f- plus . in addition, a 1 must be written into the esp/emon control bit (bit 4) in the global configuration register 013h to enable the monitor mode interface output pins. a 0 written into this control bit causes these data and clock pins to be tri-stated. lc sn lsclk lsdo lsdi addr d0 d1 d2 d3 d4 d5 d6 d7 r/w addr addr addr addr addr addr data input/output address/command byte d0 d1 d2 d3 d4 d5 d6 d7 -68 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet a 1 written to control bit rxtx (bit 3) in register 013h selects the receive side, while a 0 selects the transmit side. the framer to be monitored is selected by the value written into the two e1chcs bits (bits 1 and 0) in register 013h. for example, a value of 00 selects framer 1, and a value of 11 selects framer 4. the selected framer nrz signal is provided on output pin mondto (pin 60). the nrz receive or transmit data is clocked out on rising edges of the clock monclk (pin 61). system interface the system interface connects each of the four framers within the qe1f- plus to and from the system. the sys- tem interface is selected by one input pin and two control bits, according to the table given below. config1 pin 43 hmvip bit 2 006h mtp16m bit 1 006h system interface low 0 0 2 mbit/s transmission mode. data highway, signaling highway, 2 mhz clock and 2 ms sync pulse for each framer in both transmit and receive directions. sync pulse is positive, and one clock cycle wide. the system receive clock and sync pulse may be outputs when slip buffer is bypassed. low 0 1 16 mbit/s transmission mode, bit-interleaved. one shared data highway, 16 mhz clock and 2 ms sync pulse in both transmit and receive directions. the system receive clock and sync pulse must be inputs to the qe1f- plus . the positive sync pulses are one clock cycle wide. the slip buffers for each framer must be enabled. low 1 0 8 mbit/s transmission mode, byte-interleaved. one shared data highway, signaling highway, 16 mhz clock and 2 ms sync pulse in both transmit and receive directions. the positive sync pulses are two clock cycles wide. the system receive clock and sync pulse must be inputs to the qe1f- plus . the slip buffers for each framer must be enabled. high 0 0 2 mbit/s mvip mode: data highway, signaling highway, 2 mhz clock, and 125 microsecond sync pulse for each framer in both transmit and receive directions. the slip buffers are always enabled. the system receive and transmit clock and sync pulses are inputs to the qe1f- plus . the negative sync pulses are one clock cycle wide. high 0 1 16 mbit/s pcm highway mode, bit-interleaved. one shared data highway, 16 mhz clock and 125 microsecond sync pulse in both transmit and receive directions. the slip buffers are always enabled. the system receive and transmit clock and sync pulses are inputs to the qe1f- plus . the positive sync pulses are one clock cycle wide. high 1 0 8 mbit/s h-mvip/h.100 mode, byte-interleaved. one shared data highway, signaling highway, 16 mhz clock and 125 microsecond sync pulse in both transmit and receive directions. the slip buffers are always enabled. the system receive and transmit clock and sync pulses are inputs to the qe1f- plus . the negative sync pulses are four clock cycles wide if control bit h100 (bit 2) in regis- ter 0ffh is set to a 0 and two clock cycles wide if set to a 1. x 1 1 illegal state. do not use this combination. -69 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet for the 2 mbit/s transmission and 2 mbit/s mvip modes, each framer has separate transmit and receive inter- faces that are referred to as receive and transmit highways. each highway consists of a data bus (i.e., data highway) rdatan/tdatan, a signaling bus (i.e., signaling highway) rsigln/tsigln, a clock rclkn/tclkn, and a synchronization signal rsyncn/tsyncn. internally, each data bus is connected to a two-frame slip buffer, and each signaling bus is connected to a 120-bit signaling buffer. please note that control bits are pro- vided which enable the slip and signaling buffers to be bypassed when the 2 mbit/s transmission mode is selected. for the 8 mbit/s and 16 mbit/s transmission modes, 2 mbit/s mvip mode, 8 mbit/s h-mvip/h.100 mode and 16 mbit/s pcm highway mode, the receive and transmit slip buffers must be enabled. for the 8 mbit/s transmission mode system interface, and the 8 mbit/s h-mvip/h.100 mode system interface, common data (rdata1 and tdata1) and signaling (rsigl1 and tsigl1) buses are used to interface the four framers, as shown in figure 38. figure 38. 8 mbit/s transmission mode and 8 mbit/s h-mvip/h.100 mode system interfaces framer #1 framer #2 framer #3 framer #4 transmit signaling buffer transmit slip buffer receive slip buffer receive signaling buffer rsync1 rclk1 rdata1 rsigl1 tsync1 tclk1 tdata1 tsigl1 rx highway tx highway note: the time slots of all four framers are byte-interleaved, with separate data and signaling buses, for both receive and transmit. -70 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet for the 16 mbit/s transmission mode system interface and the 16 mbit/s pcm highway mode system inter- face, a common data bus (rdata1 and tdata1) is used to interface the four framers, as shown in figure 39. figure 39. 16 mbit/s transmission mode and 16 mbit/s pcm highway mode system interfaces framer #1 framer #2 framer #3 framer #4 transmit signaling buffer transmit slip buffer receive slip buffer receive signaling buffer rsync1 rclk1 rdata1 tsync1 tclk1 rx highway tx highway note: the time slots of all four framers are bit-interleaved, with the data and signaling combined on the data bus, for both receive and transmit. tdata1 -71 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet 2 mbit/s transmission mode the 2 mbit/s transmission mode is enabled when a low is placed on the config1 pin (pin 43), and control bits 2 (hmvip) and 1 (mtp16m) in register 006h are set to 0. transmit highway when the 2 mbit/s transmission mode is selected, the transmit highway carries information from the system to the qe1f- plus for each framer. the highway is subdivided into two time division multiplexed buses, one for data (tdatan), and the other one for signaling, alarms, and selected bits that may be multiplexed into time slot 0 (tsigln). the n in the tdatan and tsigln signals represents one of the four framers. the two buses are synchronous with respect to the highway clock (tclkn), which has a clock rate of 2048 khz. the data highway is a single bit-serial bus organized into 256-bit groups called frames, with the bits in each group num- bered 1 through 256. each frame consists of 32 time slots, numbered from 0 to 31, as shown in figure 40. also note that sixteen frames form a multiframe, with the beginning of each multiframe identified by an active high synchronization pulse (tsyncn), one (tclkn) clock cycle wide, which occurs every 2 ms, normally at the end of frame 15. the position of the tsyncn pulse is programmable to any bit position within the data bus frame using control bits tsd7-tsd0 in register 017h as described below in the transmit and receive synchroniza- tion subsection. the synchronization pulse is aligned to bit 8 in time slot 31 in frame 15 when a value of 00h is written into this register. the signaling bus (tsigln) is also divided into 256-bit frames. each signaling frame consists of 256 bits of sig- naling and alarm information for the 30 telephone data channels, numbered from 1 to 30, that are carried on the data bus (i.e., time slots 1-15 and 17-31). the first time slot (time slot 0) is assigned to carry the two international bits in bit 1 of alternate frames (bit si), and the five national bits in bits 4 through 8 and the remote alarm indication bit (a-bit) in bit 3 of alternate (nfas) frames. the positions of the time slot 0 bits in this frame are the same as found in time slot 0 of the e1 frame format. it is not required that the time slot 0 from the sig- naling bus carry the frame alignment pattern in fas frames, or have bit 2 in the alternating nfas frames set to 1. time slot 1 in the signaling bus carries the channel associated signaling (cas) multiframe format. the multiframe is repeated every 16 frames. the multiframe alignment pattern (0000), and the spare and multi- frame alarm bits (x0, y, x1, x2) occur in frame 0, followed by the abcd signaling bits for channels 1 through 30 (starting with channels 1 and 16 in frame 1, and ending with channels 15 and 30 in frame 15). the remain- ing bits, which are marked "a" in time slots 2 through 31, carry a system ais indication. status bits tuais (bit 3) and turai (bit 2) in register x14h provide the active states of the ais bit and the remote failure alarm indi- cation (rfi) bit on the transmit signaling bus in the transmission mode. these tu alarms correspond to a sys- tem sdh byte-synchronous interface. -72 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet figure 40. transmit highway - 2 mbit/s transmission mode tsyncn tclkn tdatan tsigln time slot 31 8 bits per channel notes: si = international bits r = remote alarm indication (rai) san = national bits (n = 4-8) x = don ? t care bit state y = multiframe alarm ac bc cc dc = abcd signal bits time slot 2 time slot 1 time slot 0 fas/nfas (for si/sa insertion, rai insert) s 2 s 1 s 3 s 4 s 5 s 6 s 7 s 8 aa a aaaaa a aa aa aaaa a aaaa aa frame 15 frame 2 frame 1 frame 0 one frame (256 bits) si x r sa4 sa5 sa6 sa7 sa8 si x x x x x x x for channel c (1-30) frame tsigl; s1 - s8 0 0, 0, 0, 0, x0, y, x1, x2, 1 a1, b1, c1, d1, a16, b16, c16, d16 2 a2, b2, c2, d2, a17, b17, c17, d17 3 a3, b3, c3, d3, a18, b18, c18, d18 4 a4, b4, c4, d4, a19, b19, c19, d19 5 a5, b5, c5, d5, a20, b20, c20, d20 6 a6, b6, c6, d6, a21, b21, c21, d21 7 a7, b7, c7, d7, a22, b22, c22, d22 8 a8, b8, c8, d8, a23, b23, c23, d23 9 a9, b9, c9, d9, a24, b24, c24, d24 10 a10, b10, c10, d10, a25, b25, c25, d25 11 a11, b11, c11, d11, a26, b26, c26, d26 181818 18 a = alarm bits (ais) 125 s 2 ms (multiframe) xb = spare bits (b = 0-2) even frames odd frames bit, known as ts0 a-bit -73 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet receive highway in the 2 mbit/s transmission mode, the receive highway for each framer carries information from the qe1f- plus to the system. like the transmit path, the receive highway is subdivided into two time division multiplexed buses, one for data (rdatan), and one for signaling and alarms (rsigln), where n represents one of the four framers. the two buses are synchronous with the highway clock (rclkn), which has a clock rate of 2048 khz. the clock (rclkn) is either an output to the system or an input from the system. the system clock (rclkn) or the line clock (lrclkn) may be the input clock source for the slip buffer when it is enabled. usually the system clock (rclkn) is used. the qe1f- plus sources the clock (rclkn) as an output when the slip buffer is bypassed. the receive slip buffer for a framer is disabled when a 0 is written to the rse bit (bit 3) in the framer configuration register x02h. the clock source selection is determined by the rxc bit (bit 5) in register x02h, when the signaling buffer is enabled. a 0 written into this bit position selects the system clock (rclkn) as the source clock. in addition to controlling the source of the clock, control bit rxc also controls the source of the sync pulse. the data bus is a single bit-serial bus organized into 256-bit groups called frames, as shown in figure 41. each frame consists of 32 time slots, as shown for the transmit interface. sixteen frames form a multiframe, with the beginning of each multiframe identified by an active high synchronization pulse (rsyncn), one (rclkn) clock cycle wide, which occurs every 2 ms, normally at the end of frame 15. the position of the rsyncn pulse is programmable to any bit position within the frame using control bits rsd7-rsd0 in register 018h. the synchronization pulse is aligned to bit 8 in time slot 31 in frame 15 when a value of 00h is written into this register. the signaling bus (rsigln) is also divided into 256-bit frames. each signaling frame consists of 256 bits of signaling and alarm information for the 30 data channels carried on the data bus. the first eight bits (which cor- respond to time slot 0 in the received frame) are assigned to carry the two international bits in bit 1 of alter- nate frames, and the five national bits in bits 4 through 8 and the remote alarm indication bit (a-bit) in bit 3 of alternate (nfas) frames. the other (fas) frames carry a regenerated frame alignment pattern in time slot 0. time slot 1 in the signaling bus carries the channel associated signaling multiframe format. the multiframe is repeated every 16 frames. the multiframe alignment pattern (0000), and the spare and multiframe alarm bits (x0, y, x1, x2) occur in frame 0 followed by the abcd signaling bits for channels 1 through 30 (starting with channels 1 and 16 in frame 1, and ending with channels 15 and 30 in frame 15). the remaining bits, which are marked "a" in time slots 2 through 31, carry a system ais indication. -74 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet figure 41. receive highway - 2 mbit/s transmission mode rsyncn rclkn rdatan rsigln 2 ms (multiframe) time slot 31 8 bits per channel time slot 2 time slot 1 time slot 0 fas/nfas (for si/sa insertion, rai insert) s 2 s 1 s 3 s 4 s 5 s 6 s 7 s 8 aa a aaaaa a aa aa aaaa a aaaa aa frame 15 frame 2 frame 1 frame 0 one frame (256 bits) si 1 r sa4 sa5 sa6 sa7 sa8 si 0 0 1 1 0 1 1 frame rsigl; s1 - s8 0 0, 0, 0, 0, x0, y, x1, x2, 1 a1, b1, c1, d1, a16, b16, c16, d16 2 a2, b2, c2, d2, a17, b17, c17, d17 3 a3, b3, c3, d3, a18, b18, c18, d18 4 a4, b4, c4, d4, a19, b19, c19, d19 5 a5, b5, c5, d5, a20, b20, c20, d20 6 a6, b6, c6, d6, a21, b21, c21, d21 7 a7, b7, c7, d7, a22, b22, c22, d22 8 a8, b8, c8, d8, a23, b23, c23, d23 9 a9, b9, c9, d9, a24, b24, c24, d24 10 a10, b10, c10, d10, a25, b25, c25, d25 11 a11, b11, c11, d11, a26, b26, c26, d26 notes: si = international bits r = remote alarm indication (rai) san = national bits (n = 4-8) xb = spare bits (b = 0-2) y = multiframe alarm ac bc cc dc = abcd signal bits for channel c (1-30) 181818 18 125 s a = alarm bits (ais) even frames odd frames bit, known as ts0 a-bit -75 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet 8 mbit/s transmission mode the 8 mbit/s transmission mode is enabled when a low is placed on the config1 pin (pin 43), and a 1 is writ- ten to control bit hmvip (bit 2) and a 0 is written to control bit mtp16m (bit 1) in register 006h. transmit highway when the 8 mbit/s transmission mode is selected, a common transmit highway carries information for the four framers from the system to the qe1f- plus . the single highway is subdivided into two time division multiplexed buses, one for data (tdata1), and the other (tsigl1) for signaling, alarms, and selected bits. the two buses are synchronous with respect to the single highway clock (tclk1), which has a clock rate of 16.384 mhz (two cycles per bit time). the data bus is a single bit-serial bus organized into sixteen 1024-bit frames. each frame contains byte-interleaved e1 frames of 32 time slots each for the four framers, starting with framer 1 time slot 0, followed by framer 2 time slot 0, and ending with framer 4 time slot 31, as shown in figure 42. each frame for each framer consists of thirty-two bytes, which represent the 32 time slots in an e1 frame. also note that the beginning of the 16-frame multiframe is identified by an active high, two clock cycle (tclk1) wide synchroniza- tion pulse (tsync1), which occurs every 2 ms, normally at the end of frame 16. the position of the tsync1 pulse is programmable using control bits tsd7-tsd0 in register 017h. the synchronization pulse is aligned to bit 8 in time slot 31 of framer 4 in frame 16 when a value of 00h is written into this register. the signaling bus (tsigl1) is also divided into sixteen 1024-bit frames, each consisting of 32 byte-interleaved time slots for each framer. each of the four framer ? s signaling time slots are interleaved on a byte (or time slot) boundary, starting with framer 1 time slot 0, followed by framer 2 time slot 0, and ending with framer 4 time slot 31. the format of the signaling frame is exactly the same as found in the 2 mbit/s transmission mode. figure 42. transmit highway - 8 mbit/s transmission mode 2 ms (multiframe) tsync1 tdata1 tsigl1 frame 1 frame 2 frame 3 frame 4 frame 15 frame 16 frame 1 f no. 1 f no. 2 f no. 3 f no. 4 f no. 2 f no. 3 f no. 4 dts31 dts31 dts31 dts0 dts0 dts0 dts0 f no. 1 f no. 2 f no. 3 f no. 4 f no. 2 f no. 3 f no. 4 sts31 sts31 sts31 sts0 sts0 sts0 sts0 framer number n data time slot t framer number n signaling time slot t note: the frame formats for a framer data frame (f no. n, dtst) and signaling frame (f no. n, stst) are the same as for the 2 mbit/s transmission format. 125 s -76 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet receive highway the receive highway has the same structure as the transmit highway. a common receive highway carries information for the four framers from the qe1f- plus to the system. the single highway is subdivided into two time division multiplexed buses, one for data (rdata1), and the other (rsigl1) for signaling, alarms, and selected bits. the two buses are synchronous with respect to the single highway clock (rclk1), which has a clock rate of 16.384 mhz. the data bus is a single bit-serial bus organized into sixteen 1024-bit frames. each frame contains byte-interleaved e1 frames of 32 time slots each for the four framers, starting with framer 1 time slot 0, followed by framer 2 time slot 0, and ending with framer 4 time slot 31, as shown in figure 43. the beginning of the 16-frame multiframe is identified by an active high, two clock cycle (rclk1) wide syn- chronization pulse (rsync1), which occurs every 2 ms, normally at the end of frame 16. the position of the rsync1 pulse is programmable using control bits rsd7-rsd0 in register 018h. the synchronization pulse is aligned to bit 8 in time slot 31 of framer 4 in frame 16 when a value of 00h is written into this register. the signaling bus (rsigl1) is also divided into sixteen 1024-bit frames. each frame contains byte-interleaved e1 frames of 32 time slots each for the four framers, starting with framer 1 time slot 0, followed by framer 2 time slot 0, and ending with framer 4 time slot 31. the format of a signaling frame is exactly the same as found in the 2 mbit/s transmission mode format. figure 43. receive highway - 8 mbit/s transmission mode rsync1 rdata1 rsigl1 frame 1 frame 2 frame 3 frame 4 frame 15 frame 16 frame 1 f no. 1 f no. 2 f no. 3 f no. 4 f no. 2 f no. 3 f no. 4 dts31 dts31 dts31 dts0 dts0 dts0 dts0 f no. 1 f no. 2 f no. 3 f no. 4 f no. 2 f no. 3 f no. 4 sts31 sts31 sts31 sts0 sts0 sts0 sts0 framer number n data time slot t framer number n signaling time slot t note: the frame formats for a framer data frame (f no. n, dtst) and signaling frame (f no. n, stst) are the same as for the 2 mbit/s transmission format. 2 ms (multiframe) 125 s -77 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet 16 mbit/s transmission mode the 16 mbit/s transmission mode is enabled when a low is placed on the config1 pin (pin 43), and a 0 is written to control bit hmvip (bit 2) and a 1 is written to control bit mtp16m (bit 1) in register 006h. transmit highway when the 16 mbit/s transmission mode is selected, a common time division multiplexed bus (tdata1) carries data, signaling, alarms, and selected bits in a bit-interleaved format. the bus is synchronous with respect to the single highway clock (tclk1), which has a clock rate of 16.384 mhz (one cycle per bit time). the data bus is a single bit-serial bus organized into sixteen 2048-bit frames. each frame contains bit-interleaved data and signaling bit-pairs from the e1 frames (32 time slots) of the four framers, starting with framer 1 time slot 0 data bit 1, then framer 1 time slot 0 signaling bit 1, followed by framer 2 time slot 0 data bit 1, and ending with framer 4 time slot 31 signaling bit 8, as shown in figure 44. each 16-frame multiframe is identified by an active high, one clock cycle (tclk1) wide synchronization pulse (tsync1), which occurs every 2 ms, nor- mally at the end of frame 16. the position of the tsync1 pulse is programmable using control bits tsd7- tsd0 in register 017h. the synchronization pulse is aligned to framer 4, time slot 31 signaling bit 8 in frame 16 when a value of 00h is written into this register. the formats for each of the framer ? s data frame and signal- ing frame are exactly the same as found in the 2 mbit/s transmission mode format. figure 44. transmit highway - 16 mbit/s transmission mode receive highway the receive highway has the same structure as the transmit highway. when the 16 mbit/s transmission mode is selected, a single time division multiplexed bus (rdata1) carries data, signaling, alarms, and selected bits in a bit-interleaved format for each of the four framers. the bus is synchronous with respect to the single high- way clock (rclk1), which has a clock rate of 16.384 mhz. the data bus is a single bit-serial bus organized into sixteen 2048-bit frames. each frame contains bit-interleaved data and signaling bit-pairs from the e1 frames (32 times slots) of the four framers, starting with framer 1 time slot 0 data bit 1, then framer 1 time slot 0 signaling bit 1, followed by framer 2 time slot 0 data bit 1 and ending with framer 4 time slot 31 signal- ing bit 8, as shown in figure 45. the beginning of each 16-frame multiframe is identified by an active high, one clock cycle wide (rclk1) synchronization pulse (rsync1), which occurs every 2 ms, normally at the end of frame 16. the position of the rsync1 pulse is programmable using control bits rsd7-rsd0 in register 018h. the synchronization pulse is aligned to framer 4 time slot 31 signaling bit 8 in frame 16 when a value of 00h 2 ms (multiframe) tsync1 tdata1 frame 1 frame 2 frame 3 frame 15 frame 16 f no. 1 f no. 1 f no. 2 f no. 4 f no. 4 ts31 ts31 ts0 ts0 ts0 framer number n time slot number t data/signaling bit number s bit 8 d bit 8 d bit 1 s bit 1 d bit 1 note: the frame formats for a framer data frame and signaling frame are the same as for the 2 mbit/s transmission mode. repeated 16 times 125 s -78 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet is written into this register. the formats for each of the framer ? s data frame and signaling frame are exactly the same as found in the 2 mbit/s transmission mode format. figure 45. receive highway - 16 mbit/s transmission mode 2 mbit/s mvip mode the 2 mbit/s mvip mode is enabled when a high is placed on the config1 pin (pin 43) and control bits hmvip (bit 2) and mtp16m (bit 1) in register 006h are both written with a 0. transmit highway in the 2 mbit/s mvip mode, the transmit highway for each framer in the qe1f- plus carries input information from the system. the highway for framer n is subdivided into two time division multiplexed buses, one for data (tdatan), and one for signaling (tsigln). the two buses are synchronous with the highway clock (tclkn), which has a clock rate of 2048 khz. the data bus is a single bit-serial bus organized into 256-bit groups called frames. each frame consists of thirty-two bytes, which represent the 32 time slots, as shown in figure 45. time slot 0 is used for frame alignment. time slot 16 carries either the channel associated signaling multiframe, or a clear channel. the other time slots in the frame carry the 30 telephone data channels. the frame start is identified by a synchronization pulse (tsyncn), which is one (tclkn) clock cycle wide and occurs every 125 microseconds. the position of the tsyncn pulse is programmable to any bit position within the frame using control bits tsd7-tsd0 in register 017h. the synchronization pulse is aligned to bit 1 in time slot 0 when a value of 00h is written into this register. the signaling bus (tsigln) is also divided into 256-bit frames. each signaling frame consists of 32 time slots, of which 30 time slots (1-15 and 17-31) carry the abcd signaling bits associated with the 30 telephone chan- nels. the signaling information in time slot t on the signaling bus corresponds to time slot t on the data bus. the signaling information (abcd) is carried in the last four bits of a signaling bus time slot. the first four bits in each signaling bus time slot are 0000. for time slot 16 on the signaling bus, the spare bits (x0, x1, x2) from the signaling multiframe occupy the acd bits. bit position b, which corresponds to the multiframe alarm y-bit, is ignored by the qe1f- plus . the signaling buffer is updated every other frame by the signaling information present in time slot 1 on the signaling bus. in alternating frames, time slot 0 must carry the frame alignment sequence (fas), which is a rsync1 rdata1 frame 1 frame 2 frame 3 frame 15 frame 16 f no. 1 f no. 1 f no. 2 f no. 4 f no. 4 ts31 ts31 ts0 ts0 ts0 framer number n time slot number t data/signaling bit number s bit 8 d bit 8 d bit 1 s bit 1 d bit 1 note: the frame formats for a framer data frame and signaling frame are the same as for the 2 mbit/s transmission mode. repeated 16 times 2 ms (multiframe) 125 s -79 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet framing pattern in bits 2 through 8 (0011011) and an international bit in bit 1. the other alternating frames (nfas) carry the second international bit in bit 1, a 1 in bit 2, an rai bit (a-bit) in bit 3, and five national bits in bits 4 through 8. bit 2 identifies the frame alternations for time slot 0. the state of the rai bit in time slot 0 from the system is ignored. (note: if the international, rai and sa bits are forced internally by the microproces- sor or fdl, then the ts0 may be left unformatted). the framer will always generate the fas and nfas fram- ing patterns. fas and nfas need to be inserted only if the si, san, and/or r bits from the signaling highway are to be used. figure 46. transmit highway - 2 mbit/s mvip mode receive highway in the 2 mbit/s mvip mode, the receive highway for each framer carries output information from the qe1f- plus to the system. the highway for framer n is subdivided into two time division multiplexed buses, one for data (rdatan), and one for signaling (rsigln). the two buses are synchronous with the highway clock (rclkn), which has a clock rate of 2048 khz. the data bus is a single bit-serial bus organized into 256-bit groups called frames. each frame consists of thirty-two bytes, which represent the 32 time slots, as shown in figure 47. time slot 0 is used for frame alignment. time slot 16 carries either the channel associated signaling multiframe, or a clear channel. the other time slots carry the 30 telephone data channels. the frame start is identified by a synchronization pulse (rsyncn), which is one (rclkn) clock cycle wide and occurs every 125 microseconds. the position of the rsyncn pulse is programmable to any bit position within the frame using control bits rsd7-rsd0 in register 018h. the synchronization pulse is aligned to bit 1 in time slot 0 when a value of 00h is written into this register. the signaling bus (rsigln) is also divided into 256-bit frames. each signaling frame consists of 32 time slots, of which 30 time slots (1-15 and 17-31) carry the abcd signaling bits associated with the 30 telephone chan- nels. the signaling information in time slot t on the signaling bus corresponds to time slot t on the data bus. the signaling information (abcd) is carried in the last four bits of a signaling bus time slot. the first four bits in each time slot are 0000. for time slot 16 on the signaling bus, the spare bits (x0, x1, x2) from the signaling multiframe occupy the acd bits. the multiframe alarm y-bit is carried in bit position b in time slot 16. the signaling bus is updated from the signaling buffer every frame. in alternating frames, time slot 0 carries 125 s (frame) time slot 0 time slot 1 time slot 2 time slot 31 fas/nfas 0 0 0 0abcd0 0 0 0abcd- 0 0 0abcd0 0 0 0abcd 8 bits per channel data bits for ch #1 data bits for ch #2 data bits for ch #30 abcd bits for ch #2 abcd bits for ch #30 tsyncn tclkn tdatan tsigln si 1 r sa4 sa5 sa6 sa7 sa8 si0011011 abcd bits for ch #1 frame f+1 frame f notes: si = international bits r = remote alarm indication (rai) bit, known as ts0 a-bit. san = national bits (n = 4-8) abcd = signaling bits for channel c (1-30). time slot 16 in the tsigln signals has the same format as frame 0 of the cas 18 18 18 18 18 multiframe (see figure 39). -80 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet the frame alignment sequence (fas), which is a framing pattern in bits 2 through 8 (0011011) and an interna- tional bit in bit 1. the other alternating frames carry the second international bit in bit 1, a 1 in bit 2, an rai bit (a-bit) in bit 3, and five national bits in bits 4 through 8. bit 2 identifies the frame alternations for time slot 0. figure 47. receive highway - 2 mbit/s mvip mode 125 s (frame) time slot 0 time slot 1 time slot 2 time slot 31 fas/nfas 0 0 0 0abcd0 0 0 0abcd- 0 0 0abcd0 0 0 0abcd 8 bits per channel data bits for ch #1 data bits for ch #2 data bits for ch #30 abcd bits for ch #2 abcd bits for rsyncn rclkn rdatan rsigln si 1 r sa4 sa5 sa6 sa7 sa8 si 0 0 1 1 0 1 1 abcd bits for ch #1 frame f+1 frame f 18 18 18 18 18 ch #30 notes: si = international bits r = remote alarm indication (rai) bit, known as ts0 a-bit. san = national bits (n = 4-8) abcd = signaling bits for channel c (1-30). time slot 16 in the rsigln signals has the same format as frame 0 of the cas multiframe (see figure 40). -81 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet 8 mbit/s h-mvip/h.100 mode the 8 mbit/s h-mvip/h.100 mode is enabled when a high is placed on the config1 pin (pin 43) and a 1 is written to control bit hmvip (bit 2) and a 0 to control bit mtp16m (bit 1) in register 006h. the h.100 option for the tsync1 and rsync1 pulse width is determined by control bit h100 (bit 2) in register 0ffh; if set to a 1, the frame pulse expected is two clock cycles of tclk1 or rclk1 wide; if set to a 0 a four clock cycle wide frame pulse is expected. transmit highway when the 8 mbit/s h-mvip/h.100 transmission mode is selected, a common transmit highway carries infor- mation for the four framers from the system to the qe1f- plus . the single highway is subdivided into two time division multiplexed buses, one for data (tdata1), and the other (tsigl1) for signaling and selected bits. the two buses are synchronous with respect to the single highway clock (tclk1), which has a clock rate of 16.384 mhz. the data bus is a single bit-serial bus organized into 1024-bit frames. each frame contains byte-inter- leaved e1 frames of 32 time slots each for the four framers, starting with framer 1 time slot 0, followed by framer 2 time slot 0, and ending with framer 4 time slot 31, as shown in figure 48. each frame for each framer consists of thirty-two bytes, which represent the 32 time slots in an e1 frame. also note that the frame is identified by an active low, four clock cycle (tclk1) wide synchronization pulse (tsync1), which occurs every 125 microseconds for h-mvip. for h.100 the synchronization pulse is active low, two clock cycles (tclk1) wide. the position of the tsync1 pulse is programmable using control bits tsd7-tsd0 in register 017h. the synchronization pulse is aligned with framer 4 time slot 31 bit 8 and framer 1 time slot 0 bit 1 in the next frame when a value of 00h is written into this register. the signaling bus (tsigl1) is also divided into 1024-bit frames, each consisting of 32 byte-interleaved time slots for each framer. each of the four framer ? s signaling time slots are interleaved on a byte (time slot) bound- ary, starting with framer 1 time slot 0, followed by framer 2 time slot 0, and ending with framer 4 time slot 31. the format of the signaling frame is exactly the same as found in the 2 mbit/s mvip mode. the framer will always generate the fas and nfas framing patterns. fas and nfas need to be insertedonly if the si, san, and/or r bits from the signaling highway are to be used. figure 48. transmit highway - 8 mbit/s h-mvip/h.100 mode tsync1 tdata1 tsigl1 f no. 1 f no. 2 f no. 3 f no. 3 f no. 4 f no. 1 dts0 dts31 dts31 dts0 dts0 dts0 f no. 1 f no. 2 f no. 3 f no. 3 f no. 4 f no. 1 sts0 sts31 sts31 sts0 sts0 sts0 16 clock cycles (8 bits) wide note: the data and signaling frame formats for each framer are the same as found in the 2 mbit/s mvip mode. framer number n signaling time slot number t framer number n data time slot number t 125 s 4 clock cycles (2 bits) wide (2 clock cycles wide in h.100 mode) -82 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet receive highway the receive highway has the same structure as the transmit highway. a common receive highway carries information for the four framers from the qe1f- plus to the system. the single highway is subdivided into two time division multiplexed buses, one for data (rdata1), and the other (rsigl1) for signaling and selected bits. the two buses are synchronous with respect to the single highway clock (rclk1), which has a clock rate of 16.384 mhz. the data bus is a single bit-serial bus organized into 1024-bit frames. each frame contains byte-interleaved e1 frames of 32 time slots each for the four framers, starting with framer 1 time slot 0, fol- lowed by framer 2 time slot 0, and ending with framer 4 time slot 31, as shown in figure 49. the beginning of the 1024-bit frame is identified by an active low, four clock cycle (rclk1) wide synchronization pulse (rsync1), which occurs every 125 microseconds for h-mvip. for h.100 the synchronization pulse is active low, two clock cycles (rclk1) wide. the position of the rsync1 pulse is programmable using control bits rsd7-rsd0 in register 018h. the synchronization pulse is aligned with framer 4 time slot 31 bit 8 and framer 1 time slot 0 bit 1 in the next frame when a value of 00h is written into this register. the signaling bus (rsigl1) is also divided into 1024-bit frames, each consisting of 32 byte-interleaved time slots for each framer, starting with framer 1 time slot 0, followed by framer 2 time slot 0, and ending with framer 4 time slot 31. the format of a signaling frame is exactly the same as found in the 2 mbit/s mvip mode format. figure 49. receive highway - 8 mbit/s h-mvip/h.100 mode rsync1 rdata1 rsigl1 f no. 1 f no. 2 f no. 3 f no. 3 f no. 4 f no. 1 dts0 dts31 dts31 dts0 dts0 dts0 f no. 1 f no. 2 f no. 3 f no. 3 f no. 4 f no. 1 sts0 sts31 sts31 sts0 sts0 sts0 16 clock cycles (8 bits) wide note: the data and signaling frame formats for each framer are the same as found in the 2 mbit/s mvip mode. framer number n signaling time slot number t framer number n data time slot number t 125 s 4 clock cycles (2 bits) wide (2 clock cycles wide in h.100 mode) -83 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet 16 mbit/s pcm highway mode the 16 mbit/s pcm highway mode is enabled when a high is placed on the config1 pin (pin 43) and a 0 is written to control bit hmvip (bit 2) and a 1 to control bit mtp16m (bit 1) in register 006h. transmit highway when the 16 mbit/s pcm highway mode is selected, a common transmit highway carries information for the four framers from the system to the qe1f- plus . the single highway is a single time division multiplexed bus (tdata1) that is used to carry data, signaling, and selected bits. the bus is synchronous with respect to the single highway clock (tclk1), which has a clock rate of 16.384 mhz (one cycle per bit time). the data bus is a single bit-serial bus organized into 2048-bit frames. each frame contains bit-interleaved data and signaling bit- pairs from the e1 frames (32 time slots) of the four framers, starting with framer 1 time slot 0 data bit 1, then framer 1 time slot 0 signaling bit 1, followed by framer 2 time slot 0 data bit 1, and ending with framer 4 time slot 31 signaling bit 8, as shown in figure 50. each 2048-bit frame is identified by an active high, one (tclk1) clock cycle wide synchronization pulse (tsync1), which occurs every 125 microseconds. the position of the tsync1 pulse is programmable using control bits tsd7-tsd0 in register 017h. the synchronization pulse is aligned to framer 4 time slot 31 signaling bit 8 when a value of 00h written into this register. the formats for each of the framer ? s data frame and signaling frame are exactly as found in the 2 mbit/s mvip mode format. figure 50. transmit highway - 16 mbit/s pcm highway mode receive highway the receive highway has the same structure as the transmit highway. when the 16 mbit/s pcm highway mode is selected, a single time division multiplexed bus (rdata1) carries data, signaling, and selected bits in a bit- interleaved format for each of the four framers. the bus is synchronous with respect to the single highway clock (rclk1), which has a clock rate of 16.384 mhz. the data bus is a single bit-serial bus organized into 2048-bit frames. each frame contains bit-interleaved data and signaling bit-pairs from the e1 frames (32 time slots) of the four framers, starting with framer 1 time slot 0 data bit 1, then framer 1 time slot 0 signaling bit 1, followed by framer 2 time slot 0 data bit 1 and ending with framer 4 time slot 31 signaling bit 8, as shown in figure 51. the beginning of each 2048-bit frame period is identified by an active high, one (rclk1) clock cycle wide synchronization pulse (rsync1), which occurs every 125 microseconds. the position of the rsync1 pulse is programmable using control bits rsd7-rsd0 in register 018h. the synchronization pulse is aligned to framer 4 time slot 31 signaling bit 8 when a value of 00h written into this register. the formats for each of 125 s tsync1 tdata1 f no. 4 f no. 1 f no. 1 f no. 3 f no. 4 ts31 ts31 ts0 ts0 ts31 framer number n time slot number t data/signaling bit number d bit 8 s bit 8 s bit 1 d bit 1 s bit 8 note: the frame formats for a framer data frame and signaling frame are the same as for the 2 mbit/s mvip mode. f no. 1 ts0 d bit 1 -84 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet the framer ? s data frame and signaling frame are exactly as found in the 2 mbit/s mvip mode format. figure 51. receive highway - 16 mbit/s pcm highway mode 125 s rsync1 rdata1 f no. 4 f no. 1 f no. 1 f no. 3 f no. 4 ts31 ts31 ts0 ts0 ts31 framer number n time slot number t data/signaling bit number d bit 8 s bit 8 s bit 1 d bit 1 s bit 8 note: the frame formats for a framer data frame and signaling frame are the same as for the 2 mbit/s mvip mode. f no. 1 ts0 d bit 1 -85 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet transmit and receive synchronization control bits tsd7-tsd0 in register 017h specify the number of transmit clock cycles (tclkn) that the transmit sync input signal (tsyncn) can be advanced with respect to the data and signaling signals tdatan and tsigln. the programmability is common to all four framers. the default value is 00h. the following table lists the default position of the sync pulse in relationship to the tdatan or tsigln signals. control bits rsd7- rsd0 in register 018h have a corresponding function with respect to rclkn, rsyncn, rdatan and rsigln. system interface synchronization 2 mbit/s transmission default location (00h): bit 8 in time slot 31 in frame 16. each binary value allows the sync pulse to occur one bit earlier. for example, a count of 1 corrects for a sync pulse that occurs in bit 7 instead of 8 in time slot 31 in frame 16. 8 mbit/s transmission default location (00h): framer no.4 bit 8 in time slot 31 in frame 16. each binary value in increments of 8 allows the sync pulse to occur one time slot earlier. for example, a count of 8 corrects for a sync pulse that occurs in framer no.4 bit 8 in time slot 30 in frame 16. not valid for values which are not multiples of 8. 16 mbit/s transmission default location (00h): framer no.4 signaling bit 8 in time slot 31 in frame 16. each binary value in increments of 8 allows the sync pulse to occur one time slot earlier. for example, a count of 8 corrects for a sync pulse that occurs in framer no.4 signaling bit 8 in time slot 30 in frame 16. not valid for values which are not multiples of 8. 2 mbit/s mvip default location (00h): bit 1 in time slot 0. each binary value allows the sync pulse to occur one bit earlier. for example, a count of 1 corrects for a sync pulse that occurs in bit 8 in time slot 31. 8 mbit/s h-mvip/h.100 default location (00h): framer no.4 bit 8 in time slot 31, and framer no. 1 bit 1 in time slot 0 of next frame (4 clock cycles wide). each binary value in increments of 8 allows the sync pulse to occur one time slot earlier. for example, a count of 8 corrects for a sync pulse that occurs in framer no.4 bit 8 in time slot 30 and framer no.1 bit 1 in time slot 31. not valid for values which are not multiples of 8. 16 mbit/s pcm highway default location (00h): framer no.4 signaling bit 8 in time slot 31. each binary value in increments of 8 allows the sync pulse to occur one time slot earlier. for example, a count of 8 corrects for a sync pulse that occurs in framer no.4 signaling bit 8 in time slot 30. not valid for values which are not multiples of 8. -86 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet fractional e1 capability when control bit fe1m (bit 0) in register x02h is set to a one, control bits hmvip and mtp16m (bits 2 and 1) in register 06h are set to 0, and config1 (pin 43) is low (which place all the framers in 2 mbit/s transmission mode) or high (which place all framers in 2 mbit/s mvip mode) the receive and transmit signaling highway pins become gapped clock outputs. these pins are designated rfe1gcn and tfe1gcn. individual per time slot control bits are provided for transmit and receive. control bits rfts31-rfts0 in registers x38h through x3bh, when set to one for e1 framer number n, gener- ate a gapped clock on pin rfe1gcn with 8 clock pulses per selected time slot; the first falling edge of the gapped clock can be used to sample the first bit of the selected time slot. figure 25 and figure 26 show the timing details for both receive line clock and system clock options. control bits tfts31-tfts0 in registers x3ch through x3fh, when set to one for e1 framer number n, gener- ate a gapped clock on pin tfe1gcn with 8 clock pulses per selected time slot; the first rising edge of the gapped clock occurs just before the first bit of the selected time slot. this permits a one clock cycle delay through an external device to prepare data to be sampled on the next rising edge of tclkn. figure 27 shows the timing details. control bit entslb (bit 4) in register 0ffh must also be set to 0 since control bits tfts31-tfts0 are also used to control time slot loopbacks. the following table outlines the control options for fractional e1 and time slot loopbacks. framing frame structure the basic frame structure of the 2048 kbit/s e1 signal consists of thirty-two 8-bit time slots, or 256 bits, and has a duration of 125 microseconds (8,000 frames per second). each time slot provides a 64 kbit/s channel. the thirty-two time slots are numbered 0 to 31, and the time slot bits are numbered 1 to 8. the first bit in a time slot to be received and transmitted is bit 1. framing information is carried in time slot 0, and signaling information, if it is assigned for channel associated signaling (cas), is carried in time slot 16. fe1m bit 0, x02h config1 pin 43 hmvip bit 2, 006h mtp16m bit 1, 006h entslb bit 1, 0ffh system interface rsigln/ rfe1gcn tsigln/ tfe1gcn mode 0low or high 000 2 mbit/s transmission or 2 mbit/s mvip signaling out signaling in normal 1low or high 000 2 mbit/s transmission or 2 mbit/s mvip gapped clock out gapped clock out fractional e1 0low or high 001 2 mbit/s transmission or 2 mbit/s mvip signaling out signaling in time slot loopback 1low or high 001 2 mbit/s transmission or 2 mbit/s mvip gapped clock out gapped clock out time slot loopback and fractional e1 -87 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet framing information for aligning the e1 frame is carried in time slot 0, using a two-frame sequence that alter- nates for consecutive frames. time slot 0 in the first frame carries the frame alignment pattern of x0011011. the second frame carries the pattern of x1xxxxxx, so that bit 2 identifies the first and second frames. the other bits in time slot 0, which are designated as x and are not used for frame alignment, are assigned for national, alarm and international use. the following table illustrates the framing pattern and bit assignment for time slot 0 when assigned to carry the basic framing format. where: si is reserved for international use. rai is defined as a remote alarm indication a-bit (true state is equal to 1). sa4-sa8 bits are reserved for national use. to provide additional framing protection against the emulation of a frame alignment pattern in the data stream, time slot 0 can be assigned to carry a 16-frame multiframe. the 16-frame multiframe carries a 001011 multi- frame alignment pattern, crc-4 check, and two e-bits in the bit 1 position of two sub-multiframes designated as sf i and sf ii, as shown below: where: c1-c4 are the crc-4 bits. rai is defined as a remote alarm indication a-bit (true state is equal to 1). sa4-sa8 are reserved for national use. e-bits are used for a crc-4 error indication framebit 12345678 1 si (#1) 0011011 2 si (#2) 1 rai sa4 sa5 sa6 sa7 sa8 sub-fframebit 12345678 sf i 0 c1 0011011 1 0 1 rai sa4 sa5 sa6 sa7 sa8 2 c2 0011011 3 0 1 rai sa4 sa5 sa6 sa7 sa8 4 c3 0011011 5 1 1 rai sa4 sa5 sa6 sa7 sa8 6 c4 0011011 7 0 1 rai sa4 sa5 sa6 sa7 sa8 sf ii 8 c1 0011011 9 1 1 rai sa4 sa5 sa6 sa7 sa8 10 c2 0011011 11 1 1 rai sa4 sa5 sa6 sa7 sa8 12 c3 0011011 13 e 1 rai sa4 sa5 sa6 sa7 sa8 14 c4 0011011 15 e 1 rai sa4 sa5 sa6 sa7 sa8 -88 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet frame alignment the qe1f- plus supports two frame alignment operating modes in each framer: basic frame alignment detec- tion, and frame alignment detection with a crc-4 validation. the receive framer circuit also employs an offline framing algorithm, where the payload is sent to the terminal side output even during loss of frame (together with rsync and rclk, if these are framer outputs). this is advantageous, since re-framing usually occurs at the same frame position. basic frame alignment detection has two algorithms: standard and frame hold-off. the selection is deter- mined by control bit bfaa (bit 5) in the framer configuration register (x04h) for each framer. when control bit bfaa is written with a 0, the standard algorithm is selected. when written with a 1, the frame hold-off algorithm is selected. the standard framing algorithm operates continuously according to the following steps: - a valid frame alignment signal x0011011 is detected in time slot 0 of frame f (fas frame). - the absence of a frame alignment signal is verified by checking that bit 2 is a 1 in time slot 0 of frame f+1 (nfas frame). - a valid frame alignment signal x0011011 is detected in time slot 0 of frame f+2 (fas frame). if these criteria are met by three consecutive frames, then the framer is declared to be aligned. thereafter, if any step fails at frame x, a new search for frame alignment is started in the next bit position of frame x. the frame hold-off algorithm uses the same steps as found in the standard frame alignment search, except that the new search is initiated in the next bit position in frame x+2. the qe1f- plus also supports frame alignment detection by validating a crc-4 multiframe check sequence in addition to either of the basic frame alignment detection sequences. each framer in the qe1f- plus can be configured for two types of crc-4 multiframe check: manual or an automatic mode. the manual mode is selected by writing a 0 to control bit crca (bit 3) in register x04h. in the manual mode, after frame alignment has been achieved, multiframe alignment occurs if two valid crc multiframe signals are detected within 8 mil- liseconds (see table above). after crc multiframe is established the qe1f- plus begins checking the crc bits. if multiframe cannot be achieved within the 8 millisecond period and control bit crca is set to a 1, a new search for frame alignment is initiated, and an out of crc-4 multiframe status indication (oocrcm) is declared (bit 3 in register x1bh). when control bits crcmd1 and crcmd0 (bits 2 and 1) in register x04h are set to 10, an indication of crc-4 multiframe alignment loss is sent to the distant end by setting the two e-bits in time slot 0 to zero. the automatic mode is selected by writing a 1 to control bit crca (bit 3) in register x04h. if multiframe is not found by the process described above within a 400 millisecond search period, the framer assumes that the dis- tant end is not configured for crc multiframe pattern, and sets a status bit, ncrc4 (bit 7) in register x1bh. the qe1f- plus then inhibits further crc-4 processing. when control bits crcmd1 and crcmd0 (bits 2 and 1) in register x04h are set to 10, an indication of crc-4 multiframe alignment loss is sent to the distant end by setting the two e-bits in time slot 0 to zero. for isdn applications (itu-t i.431 or ets 300 011), the automatic mode selected by writing a 1 to control bit crca (bit 3) in register x04h may be altered by setting control bit aags (bit 3) in global register 0ffh to a 1. the basic differences are that: 1) rai in time slot 0 is set to a 1 if multiframe alignment is not found in the 8 millisecond period and then returned to 0 if basic frame alignment is still present and a new search is initiated; 2) the e-bits are set to a 1 and only reset to indicate crc-4 errors once multiframe alignment has been achieved; and 3) the qe1f- plus never stops searching for multiframe alignment. if multiframe alignment is not achieved in 100 to 500 milliseconds (status bit oocrcm (bit 3) in register x1bh remains a 1) the control bit raie (bit 2) in register x07h should be set to a 1 until oocrcm becomes a 0. for ets 300 011 this sends a required remote alarm indication to the far end indicating failure to achieve multiframe alignment. the crc-4 pattern is checked, and an excessive crc error indication ecrce (bit 6) in register x1bh is set when 915 or more of the last 1000 crcs were received in error. ecrce is cleared after basic frame alignment is regained. the following table summarizes the control bits associated with selection of the frame alignment algorithm for one of the four framers -89 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet . crcmd1 x04h:2 crcmd0 x04h:1 bfaa x04h:5 crca x04h:3 action 0 0 x x transparent (unframed mode). frame alignment detector is bypassed. please note that the slip buffers and signaling buffers are also disabled in this mode. 0 1 0 x frame alignment detector is enabled using the standard algorithm. the crc-4 multiframe detector and generator are disabled. 0 1 1 x frame alignment detector is enabled using the frame hold- off algorithm. the crc-4 multiframe detector and generator are disabled. 1000frame alignment detector is enabled using the standard algorithm. the crc-4 multiframe detector and generator are enabled for manual operation. in addition, the receive 10-bit crc counter is enabled. the transmit e-bits are sent as zeros when the crc-4 multiframe is lost. the 10-bit e-bit performance counter is also enabled, to count e-bit errors. 1010frame alignment detector is enabled using the frame hold- off algorithm. the crc-4 multiframe detector and generator are enabled for manual operation. in addition, the receive 10-bit crc counter is enabled. the transmit e-bits are sent as zeros when the crc-4 multiframe is lost. the 10-bit e-bit performance counter is also enabled, to count e-bit errors. 1001frame alignment detector is enabled using the standard algorithm. the crc-4 multiframe detector and generator are enabled for automatic operation. in addition, the receive 10- bit crc counter is enabled. transmit e-bits are sent as zero when crc-4 multiframe is lost. the 10-bit e-bit performance counter is also enabled for counting e-bit errors. 1011frame alignment detector is enabled using the frame hold- off algorithm. the crc-4 multiframe detector and generator are enabled for automatic operation. in addition, the receive 10-bit crc counter is enabled. the transmit e-bits are sent as zero when crc-4 multiframe is lost. the 10-bit e-bit per- formance counter is also enabled for counting e-bit errors. 1100frame alignment detector is enabled using the standard algorithm. the crc-4 multiframe detector and generator are enabled for manual operation. in addition, the receive 10-bit crc counter is enabled. the e-bits are always transmitted as 1s, and the 10-bit e-bit performance counter is disabled. 1110frame alignment detector is enabled using the frame hold- off algorithm. the crc-4 multiframe detector is enabled for manual operation. in addition, the receive 10-bit crc counter is enabled. the e-bits are always transmitted as 1s, and the 10-bit e-bit performance counter is disabled. -90 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet loss of frame alignment an out of frame (oof) alarm is declared when a selected number of consecutive incorrect frame alignment patterns in time slot 0 is detected, or when 915 or more out of 1000 crc-4 are received in error (ecrce, bit 6 in register x1bh). the oof alarm is indicated at bit 5 in register x10h. an incorrect frame alignment pattern is defined as an incorrect bit in at least one of the seven framing bits in an fas time slot 0, or an error (i.e., a 0) in bit 2 in time slot 0 in the next (nfas) frame. the number of incorrect frame alignment patterns in error is programmable using the oof1 and oof0 control bits (bits 7 and 6) in register x04h. the out of frame align- ment condition starts the resynchronization process for frame alignment. in addition, the software can also ini- tiate a resynchronization of the frame alignment detector by writing a one to control bit rsyc (bit 0) in register x04h. the following table lists the selection options for declaring an out of frame (oof) alarm. loss of crc-4 multiframe alignment when the crc-4 feature is enabled, a crc-4 loss of multiframe indication oocrcm (bit 3 in register x1bh) is generated when basic frame alignment is lost either by consecutive incorrect frame alignment patterns or by 915 or more out of 1000 crc-4 received in error, as indicated by the oof alarm, bit 5 in register x10h. the oocrcm bit is cleared only when multiframe alignment is regained. transmit framer each of the four transmit framers performs the following functions, unless the framer is configured for the transparent (unframed) mode of operation using the 2 mbit/s transmission mode interface only: - generates the framing pattern (x0011011) in alternating (fas) frames for time slot 0. 1101frame alignment detector is enabled using the standard algorithm. the crc-4 multiframe detector and generator are enabled for automatic operation. the e-bits are always transmitted as 1s. the crc-4 counter is enabled. 1111frame alignment detector is enabled using the frame hold- off algorithm. the crc-4 multiframe detector and generator are enabled for automatic operation. the e-bits are always transmitted as 1s. the crc-4 counter is enabled. oof1 x04h:7 oof0 x04h:6 action 0 0 three consecutive incorrect frame alignment patterns in the seven-bit framing sequence in an fas time slot 0. 01 four consecutive incorrect frame alignment patterns in the seven-bit framing sequence in an fas time slot 0. 1 0 three consecutive incorrect frame alignment patterns in the seven-bit framing sequence in an fas time slot 0, or three consecutive incorrect bit 2 values of 0 in a nfas time slot 0. 1 1 four consecutive incorrect frame alignment patterns in the seven-bit framing sequence in an fas time slot 0, or four consecutive incorrect bit 2 values of 0 in a nfas time slot 0. crcmd1 x04h:2 crcmd0 x04h:1 bfaa x04h:5 crca x04h:3 action -91 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet - sets bit 2 to 1 in time slot 0 in (nfas) frames not carrying the framing pattern. - inserts either the international bits for the basic format, or the crc-4/e-bits into time slot 0. - inserts the national bits, and remote alarm indication bit, into nfas time slot 0. - inserts time slots 1-15 and 17-31 into the transmitted frame. - inserts time slot 16 as either a clear channel, or channel associated signaling information. the transparent mode is not valid for other system interface highway modes. these five modes require the slip buffers and framed mode to be enabled. please note that when a framer is configured for the transparent mode, all the time slots in the frame are transmitted from the data bus transparently through the qe1f- plus , bypassing the slip buffer. time slot 0 the basic framed mode of operation is selected by writing control bits crcmd1 (bit 2) and crcmd0 (bit 1) in register x04h to 01. the selection is common to both the transmit and receive sides of a framer channel. the international bits from the transmit signaling highway are inserted into bit 1 of time slot 0, unless the crc-4 feature is selected. the microprocessor can disable this path by writing a 0 to control bit tsis (bit 7) in register x2ch, which freezes the values of the two international bits, located at bit 7 in registers x90h and xb0h, and allows them to be written by the microprocessor. the crc-4 framing mode is selected by writing control bits crcmd1 (bit 2) and crcmd0 (bit 1) in register x04h to 10 or 11. the insertion of the international bits from the signaling highway is disabled, and the transmit framer inserts the calculated crc-4 value and the e-bits. the e-bit generation is internal to the framer within the qe1f- plus , and is not accessible by the microprocessor in the transmit direction. when control bit aags (bit 3) in register 0ffh is set to a 1, one e-bit may be set to 0 immediately after the qe1f- plus frames up even though the first crc-4 is correct. the crc multiframe alignment pattern is generated by the framer. the time slot 16 (ts16) multiframe align- ment pattern is generated only when either the cas or cas-inverted signaling types are selected (bits 7 and 6) in register x03h. ts16 multiframe alignment is meaningless in ts16 clear channel mode. ts16 multiframe alignment is independent of device mode. the remote alarm indication (rai) a-bit is assigned to bit 3 in alternating frames in both the framed and crc-4 mode of operation. when control bit autrai (bit 6) in register x1ah is set to 1, a loss of frame alignment on the receive side sets the transmitted rai bit to 1 for the duration of the alarm. the microprocessor can also write the state of the rai bit, independent of automatic rai insertion. when the microprocessor writes a 1 to control bit raie (bit 2) in register x07h, the rai bit is transmitted as a 1. in addition, when control bit ensrai (bit 4) in register x00 is written with a 1, a 1 in bit rfi (bit 3) in time slot 0 from the signaling highway in the transmission mode only will also result in an rai alarm being transmitted. the rai alarm from the system highway is designated as a remote failure indication (rfi). the transmitted path for the individual national bits (sa4 to sa8) in time slot 0 in either framing mode can be assigned from the hdlc link or from the signaling highway. when control bit bnal (bit 1) in register x01h is a 1, all the national bits are transmitted from the signaling highway via a buffer. the microprocessor can disable any of the national bits by writing a 0 to one more control bits tsa4s-tsa8s (bits 4-0) in register x2ch and insert the software values for sa4-sa8 into the transmitted bits by writing the values to bits 4-0 in register xb0h. this is the recommended method of fixing the sa bits to a specific value per g.704. when control bit bnal is written with a 0, the transmitted path will be either via the data link or via the signaling highway through the buffer. the bandwidth of the hdlc channel is controlled by control bits sa4-sa8 (bits 4-0) in reg- ister x0ch. a 1 written to one or more bits selects those bits as the hdlc channel. for example, if control bits sa4-sa7 are set with a 1, then bits sa4 to sa7 in time slot 0 will transmit the hdlc channel. the sa8 bit time slot 0 path will be from the signaling highway via the buffer. when a 1 is written to control bits sa4-sa8 and control bit bnal is set to a 0, hdlc flag characters are continuously sent in the national bits selected regardless of the setting of control bit eht (bit 6) in register x08h. the seven-bit framing pattern (x0011011) in alternating (fas) frames for time slot 0, and the 1 value for bit 2 -92 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet in time slot 0 in (nfas) frames not carrying the framing pattern (x1xxxxxx), are generated by the framer. each framer also has the capability of generating framing pattern errors in fas frames, bit 2 errors in alternat- ing (nfas) frames, and crc-4 errors. when control bit fase (bit 3) in register x07h is set to 1, the transmit- ter sends the frame alignment pattern (in fas time slot 0 in alternating frames) in error continuously. all the bits in the frame alignment sequence are inverted (x0011011 becomes x1100100). the frame alignment sequence error condition is transmitted until this bit is written with a 0. when control bit nfase (bit 4) in x06h is set to 1, the transmit framer sends bit 2 (in nfas time slot 0 in alternating frames) as a 0. bit 2 in time slot 0 of the nfas frames is transmitted in error as a 0 until this bit is written with a 0. when control bit crc (bit 4) in register x07h is set to 1, the crc-4 bits in time slot 0 are transmitted in the inverted state once. to send another crc-4 error, this bit must be first written with a 0, and then a 1. time slot 16 time slot 16 may be assigned for channel associated signaling or as a clear channel. different modes of channel associated signaling are selected when control bits typ1 and typ0 (bits 7 and 6) in register x03h are equal to 01, 10, or 11. when control bits typ1 and typ0 are equal to 00, time slot 16 is designated as a clear channel, and the transmitted path is from the data bus. the selection is common for the receive side of the same framer (n = x). channel associated signaling is inserted into time slot 16 of the transmitted frame from the signaling highway via buffer locations when the buffer is enabled, or directly from the signaling highway when it is bypassed (2 mbit/s transmission mode option only). the buffer location for reading the multiframe pattern, spare bits, and multiframe alarm is register xd0h. the buffer locations for the abcd bits of the signaling channels are regis- ters xd1h through xdfh. the signaling channel (i.e., abcd signaling bits) states can be frozen by writing a 1 to control bit txf (bit 4) in register x03h. the contents of an individual signaling channel (c = 1-30) in buffer locations xd1h through xdfh can be frozen by writing a 0 to one or more of control bits se1-se30 in regis- ters xe8-xebh. when signaling channel c is frozen, the transmitted signaling state is the value sitting in the buffer at the time the sec bit was set to 0. the microprocessor can write a new signaling state, or a service code, for the frozen channel. frame 0 in the 16-frame multiframe carries the 4-bit multiframe pattern, 3 spare bits, and the remote multi- frame alarm. the qe1f- plus regenerates the multiframe alignment pattern. these bits from the signaling high- way can be read by the microprocessor in register xd0h. however, the value sitting in the transmit signaling buffer cannot be frozen, and a new value substituted for it. a loss of multiframe alignment will result in a remote multiframe alarm being transmitted when control bit auty (bit 7) in register x1ah is a 1. in addition, the micro- processor can also generate a remote multiframe alarm by writing a 1 to control bit ts16ye (bit 5) in register x06h. time slots 1-15 and 17-31 the time slots 1-15 and 17-31 are inserted into the transmitted frame from the slip buffer when it is enabled, or directly from the data highway when it is bypassed (2 mbit/s transmission mode only). the slip buffer loca- tions are registers x91h - xafh (frame 1) and xb1h - xcfh (frame 2). an individual time slot in the buffer can be frozen by writing a 0 to one or more control bits tde1-tde31 in registers xe4h - xe7h. this permits the microprocessor to write idle or service codes for one or more framers. fast sync mode the qe1f- plus provides a fast sync mode which may be used for testing purposes. the fast sync mode for the receiver side is selected when control bit rxfs (bit 1) in register x06h is written with a 1 in the nrz mode. a pulse that is one clock cycle wide in bit position 256 of the last frame in the crc-4 multiframe forces the framer into synchronization. it can occur repetitively at 2 ms intervals, or it can be pulsed once provided the received framing sequence is valid afterwards. the fast sync mode for the transmitter side is selected when control bit txfs (bit 0) in register x06h is written -93 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet with a 1 in the nrz mode. the tfsn output in this mode is a one clock cycle wide pulse in bit position 256 of the last frame in the crc-4 multiframe that occurs every 2 ms. this allows an external device to be synchro- nized to the qe1f- plus framer. slip buffers each framer contains a two-frame slip buffer in both the transmit and receive data directions. either of the slip buffers can be bypassed, if required, in the 2 mbit/s transmission mode only. the slip buffers must be enabled in the 2 mbit/s mvip mode, the 8 mbit/s h-mvip/h.100 mode, the 16 mbit/s pcm highway mode, and the 8 mbit/s and 16 mbit/s transmission modes. only the transmit and receive data time slots (time slots 1-15 and 17-31) are passed through the slip buffers. channel 16 may also be present in the slip buffer when it assigned as a clear channel. the signaling channel in time slot 16 and selected bits in time slot 0 are buffered in a separate memory location and are not subjected to slips. each buffer is organized as a circular queue two frames in length. at this point, if data is arriving faster than it is being removed, the buffer will begin to fill. before the buffer becomes totally full, a controlled slip will occur and one frame of data will discarded. this is accomplished by moving the write pointer back one frame and overwriting the previous frame that was written. if, after recentering, the data is being removed faster than it is arriving, the buffer will begin to empty. before the buffer becomes completely empty, a controlled slip occurs in the opposite direction, and a frame of data is added to the buffer. this is accomplished by moving the read pointer back one frame and repeating the last frame sent. each buffer may be manually recentered by setting the tsr or rsr control bits (bit 2 and 1) in the framer clock control register x02h. the transmit slip buffer is used to absorb low speed jitter in the transmit direction. the transmit slip buffer is enabled by writing a 1 to control bit tse (bit 4) in the framer clock control register x02h. when enabled, time slots are written into the transmit slip buffer by the system clock (tclkn), and read out by the recovered receive clock (lrclkn) or the local oscillator (lo). control bits txc1 and txc0 (bits 7 and 6) in x02h select the clock source. the time slots (t = 1-31) from the transmit data bus are written into the slip buffer when their respective enable bits (tdet) in registers xe4h, xe5h, xe6h, and xe7h are written with a 1. a phase shift between the two clocks is detected, and the deletion or repetition of one frame of data (31 time slots, or 30 time slots if time slot 16 signaling is enabled) occurs if the buffer reaches an almost full or almost empty threshold. a transmit slip error is indicated by status bit txslip (bit 1) in register x10h, with a latched event ltxslip (bit 1) indicated in x11h. the transmit slip buffer status is indicated by reading status bits txs1 and txs0 (bits 7 and 6) in register x14h. -94 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet the individual time slots in both frames can be accessed by the microprocessor, as well as written by the microprocessor in place of data. when a time slot enable control bit in register location xe4-xe7h is written with a 0, the content of the two-frame slip buffer location is frozen. the microprocessor can write an idle or ser- vice code to be transmitted to the line. the transmit slip buffer data locations are x91h (time slot 1) to xafh (time slot 31) for frame 1, and xb1h (time slot 1) to xcfh (time slot 31) for frame 2. please note that both buffer locations (i.e., frame 1 and frame 2) must be written with the service or idle code. a simplified schematic of the transmit slip buffer is shown in figure 52. figure 52. transmit slip buffer tr a n s m i t slip buffer slip buffer control 0 1 0 1 2 divide by 256 tse (bit 4 in x02h) transmit data txc1, txc0 lo tclkn lrclkn synchronization tsr note: n is the framer number (1, 2, 3, 4) (bit 2 in x02h) tclkn tdatan tsyncn qe1f- plus (local oscillator) (control bits, bits 7 and 6 in x02h) framer n -95 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet the receive buffer is used when the receive clock (rclkn) is provided from an external source. the receive slip buffer controls the time slot access and retiming, providing a two-frame buffer that is optionally bypassable in the 2 mbit/s transmission mode only. the slip buffer must be enabled in the other system highway modes. time slots from the line interface are written into the slip buffer by the recovered receive clock (lrclkn), and read out by the system clock (rclkn). a phase shift between the two clocks is detected, and deletion or repe- tition of one frame of data (31 time slots, or 30 time slots if time slot 16 signaling is enabled) occurs if the buffer reaches an almost full or almost empty threshold. the time slots from the receive line signal are written into the slip buffer when their respective enable bits (rden) in registers xe0h, xe1h, xe2h, and xe3h are written with a 1. individual time slots can be accessed by the microprocessor, and they can be written by the microprocessor in place of data. when a time slot enable control bit in register location xe0-xe3h is written with a 0, the content of the two-frame slip buffer location is frozen. the microprocessor can write an idle or service code in the loca- tion that will be transmitted to the receive data highway. the receive slip buffer data locations are x41h (time slot 1) to x5fh (time slot 31) for frame 1, and x61h (time slot 1) to x7fh (time slot 31) for frame 2. please note that both buffer locations (i.e., frame 1 and frame 2) must be written with the service or idle code. a sim- plified schematic of the receive slip buffer is shown in figure 53. a receive slip error is indicated by status bit rxslip (bit 0) in register x10h, with a latched event lrxslip (bit 0) indicated in x11h. the receive slip buffer status is indicated by reading status bits rxs1 and rxs0 (bits 5 and 4) in register x14h. figure 53. receive slip buffer receive slip buffer slip buffer control 0 1 rdatan rsr note: n is the framer number (1, 2, 3, 4) (bit 1 in x02h) rclkn receive data rsyncn qe1f- plus rse rxc (bit 5 in x02h) lrclkn recovered sync (bit 3 in x02h) framer n -96 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet throughput delay delay through the qe1f- plus is a function mainly of the slip buffers, though other factors also influence the amount of delay. the table below gives the typical delay for different elements of the framer from line to system and from system to line. all numbers are in bit times for a clock rate of 2048 khz (i.e., 488 ns). to estimate the total delay through a framer, add the system interface delay to the slip buffer delay and the codec delay (choose nrz, ami or hdb3 value) and the framing mode delay, and then multiply by 488 ns. notes: 1. when the framer is reset, the nominal delay is 128 bits through the slip buffer. recenter (control bit rsr toggled) will cause a slip if the delay exceeds 384 bits, to minimize the delay. 2. when the framer is reset, the nominal delay is 128 bits through the slip buffer. recenter (control bit tsr toggled) will cause a slip if the delay exceeds 384 bits, to minimize the delay. signaling there are two types of signaling schemes used for the e1 telephone channels: common channel signaling (ccs), and channel associated signaling (cas). common channel signaling, such as ccs no. 7, can be assigned to be carried in one or more of the time slots, including time slot 16. the qe1f- plus does not pro- cess any part of the common channel signaling format. instead, it is passed transparently through the system to the data bus. the clear channel capability for time slot 16 is selected when control bits typ1 and typ0 (bits 7 and 6) in register x03h are written with 00. time slot 16 may be used to carry channel associated signaling. the channel associated signaling feature is selected when control bits typ1 and typ0 (bits 7 and 6) in register x03h are written with a value other than 00. the signaling information is carried as abcd signaling bits that are associated with time slots 1 through 15, and 17 through 31. a sixteen-frame format, referred to as a signaling multiframe, is used to carry the sig- naling information. please note that the signaling multiframe is arbitrary with respect to the multiframe structure carried in time slot 0. the following table shows the signaling multiframe structure for time slot 16. direction of signal flow system interface slip buffer (select one) codec (select one) framing mode (select one) disabled enabled nrz ami hdb3 framed modes transparent mode line to system rposn/rldatn to rdatan 0.5 1 8 to 504 (note 1) 002 2.5 0 system to line tdatan to tposn/tldatn 0.5 0 8 to 504 (note 2) 002 6 0.5 framebit 12345678 0 0 000x0yx1x2 1 a1 b1 c1 d1 a16 b16 c16 d16 2 a2 b2 c2 d2 a17 b17 c17 d17 3 a3 b3 c3 d3 a18 b18 c18 d18 4 a4 b4 c4 d4 a19 b19 c19 d19 5 a5 b5 c5 d5 a20 b20 c20 d20 -97 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet where: ac, bc, cc, dc represent the signaling information associated with the telephone channel number (c = 1-30). channel 1 corresponds to time slot 1, while channel 16 corresponds to time slot 17, since time slot 16 is assigned to carry the signaling information. the y-bit is used for a multiframe alarm indication. a 1 indicates an alarm. the x0, x1 and x2 spare bits are not used, and are normally set to 1. channel associated signaling multiframe alignment the qe1f- plus supports two cas multiframe alignment operating modes for each framer: standard, or enhanced. the standard algorithm is selected by writing a 0 to control bit casa (bit 4) in register x04h. the enhanced algorithm is selected when a 1 is written to the control bit casa. the standard multiframe alignment algorithm is compatible with itu-t recommendation g.732. standard channel associated signaling multi- frame alignment is declared when the qe1f- plus detects a 0000 pattern in bits 1 to 4 in time slot 16 and this was preceded by a time slot 16 with a non-zero pattern in bits 1-4. for the enhanced algorithm, multiframe alignment is declared only when the 0000 pattern is found after the previous 15 frames contained a time slot 16 that did not carry the 0000 pattern in bits 1-4. the status bit ts16me (bit 4) in register x1bh is assigned for a multiframe error indication for each framer. when a 1 is written to control bit enoo16m (bit 2) in register x1ah, ts16me is used to provide unlatched and latched status indications at oomf (bit 2) in register x10h and loomf (bit 2) in register x11h. the ts16me status indication is set when any of the following conditions occurs: - the 4-bit all zero pattern (bits 1-4) in time slot 16 is lost for two consecutive multiframes. - time slot 16 is all zeros for 16 consecutive frames. - frame alignment is lost (oof alarm) control bits typ1 and typ0 (bits 7 and 6) in register x03h may be written to 01, to prevent the far end framer from falsely achieving cas multiframe alignment if signaling bits ac bc cc dc = 0000. the qe1f- plus will automatically replace the 0000 code with 1111 prior to insertion into time slot 16 for transmission. signaling buffers 120-bit transmit and receive signaling buffers are used to interface the qe1f- plus to the system. in the receive direction, the signaling bits are extracted from the data stream and placed in the receive signaling buffer after the multiframe sequence is detected in the receive framer block. a simplified schematic of the receive signal- 6 a6 b6 c6 d6 a21 b21 c21 d21 7 a7 b7 c7 d7 a22 b22 c22 d22 8 a8 b8 c8 d8 a23 b23 c23 d23 9 a9 b9 c9 d9 a24 b24 c24 d24 10 a10 b10 c10 d10 a25 b25 c25 d25 11 a11 b11 c11 d11 a26 b26 c26 d26 12 a12 b12 c12 d12 a27 b27 c27 d27 13 a13 b13 c13 d13 a28 b28 c28 d28 14 a14 b14 c14 d14 a29 b29 c29 d29 15 a15 b15 c15 d15 a30 b30 c30 d30 framebit 12345678 -98 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet ing buffer is shown in figure 54. in the 2 mbit/s, 8 mbit/s and 16 mbit/s transmission modes, eight signaling bits are sent each frame. receive signaling bits are clocked out by the system clock (rclkn), which is sourced by either the system or the qe1f- plus . the signaling bits on rsigln are sent such that they will meet the system requirements for formatting a tributary unit (tu) in an sdh format in the next multiframe. these bits can be extracted using the receive sync signal rsyncn. in the 2 mbit/s mvip mode, the 8 mbit/s h-mvip/ h.100 mode and the 16 mbit/s pcm highway mode, all the signaling bits are sent for every framer every frame (125 microseconds) from the receive signaling buffer by using the system clock (rclkn) and sync pulse (rsyncn). figure 54. receive signaling buffer the received signaling bits are stored sequentially in the receive signaling buffer in the order they are received. the storage sequence starts with 0 0 0 0 x0 y x1 x2 (in x80h), followed by a1 b1 c1 d1 a16 b16 c16 d16 (in x81h) and so on, ending with a15 b15 c15 d15 a30 b30 c30 d30 (in x8fh). the signaling bits in the receive signaling buffer (register locations x80h-x8fh) may be read at any time by the microprocessor in order to monitor the signaling states, or to modify the outgoing values. since the buffer is accessed by multiple asynchronous processes, the read and write cycles for the signaling buffer are synchronous to the internal clocks. simultaneous accesses are serviced sequentially. the priority of service depends on the amount of latency acceptable between when the request was received and when the data is required to be available. when the corresponding (receive and transmit) signaling enable bits (se1-se30 bits) in register locations xe8h (channels 1 - 8), xe9h (channels 9 - 16), xeah (channels 17 - 24), and xebh (channels 25 - 30) are written with a 1, the signaling bits are sent on the signaling highway (and data highway) in time slot 16. for example, a 1 written to control bit se1 enables the signaling bits for channel 1 to be written into the signaling buffer. when a 0 is written into control bit se1, the signaling buffer for channel 1 signaling is frozen. the frozen states will be sent on the signaling highway until the se1 bit is written with a 1 or the microprocessor writes a new value into bits a1b1c1d1 (bits 7-4) in register location x81h. the hex value written into register x81h for bits 3-0 (signaling for a16 b16 c16 d16) will be ignored by the qe1f- plus unless the se16 bit is set to 1. the signaling bits in the receive direction are automatically frozen in their present states when loss of signal or loss of synchronization occurs. a signaling freeze may also be initiated manually by writing a 1 to control bit rxf (bit 5) in register x03h. a receive signaling freeze indication is given by status bit rxsf (bit 7) in register x15h. parallel to serial read address rx signaling ram data addr write address from framing hardware recovered rxsync recovered rxfsync cpu data cpu addr rclkn rsyncn rsigln 4 5 5 5 5 note: n is the framer number (1, 2, 3, 4) qe1f- plus framer n i/o -99 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet a simplified schematic of the transmit signaling buffer is shown in figure 55. transmit signaling bits on the sig- naling pin tsigln are clocked into the transmit signaling buffer using the transmit system clock tclkn and sync pulse tsyncn. in the 2 mbit/s, 8 mbit/s, and 16 mbit/s transmission modes, eight signaling bits are pro- vided each frame. in the 2 mbit/s mvip mode, the 8 mbit/s h-mvip/h.100 mode and the 16 mbit/s pcm high- way mode, all signaling bits are exchanged for every channel every frame (125 microseconds). figure 55. transmit signaling buffer the transmit signaling bits from the signaling highway are stored sequentially in the transmit signaling buffer in the order they are received. the storage sequence starts with 0 0 0 0 x0 y x1 x2 (in xd0h), a1 b1 c1 d1 a16 b16 c16 d16 (in xd1h) and so on, ending with a15 b15 c15 d15 a30 b30 c30 d30 (in xdfh). the signaling bits in the transmit signaling buffer (register locations xd0h-xdfh) may be read at any time by the micropro- cessor in order to monitor the signaling states, or to modify the outgoing values. since the buffer is accessed by multiple asynchronous processes, the read and write cycles for the signaling buffer are synchronous to the internal clocks. simultaneous accesses are serviced sequentially. the priority of service depends on the amount of latency acceptable between when the request was received and when the data is required to be available. when the corresponding signaling enable bits (se1-se30 bits) in register locations xe8h (channels 1 - 8), xe9h (channels 9 - 16), xeah (channels 17 - 24), and xebh (channels 25 - 30) are written with a 1, the signaling bits are written into the transmit signaling buffer. for example, a 1 written to control bit se1 enables the signaling bits from the signaling highway for channel 1 to be written into the signaling buffer. when a 0 is written into control bit se1, the signaling buffer for channel 1 signaling is frozen. the frozen states will be transmitted until the se1 bit is written with a 1 or the microprocessor writes a new value into bits a1b1c1d1 (bits 7-4) in register xd1h. the hex value written into register xd1h for bits 3-0 (signaling for a16 b16 c16 d16) is ignored by the qe1f- plus unless the se16 bit is set to 1. the actual generation of the y-bit to the transmit line is activated by [ts16ye or (oomf and auty)] where ts16ye is bit 5 of x06h, oomf is the detection of loss of multiframe (bit 2 of register x10h) and auty is bit 7 of x1ah. a transmit signaling freeze indication occurs when control bit txf (bit 4) in register x03h is written with a 1 (manual freeze), or when ais is detected on the signaling highway (2 mbit/s, 8 mbit/s, and 16 mbit/s transmis- sion modes only). a transmit signaling freeze indication is given by status bit txsf (bit 6) in register x15h. serial to parallel write address tx signaling ram data addr read address to framing hardware txsync txfsync cpu data cpu addr tclkn tsyncn tsigln 4 5 5 5 5 note: n is the framer number (1, 2, 3, 4) qe1f- plus framer n i/o -100 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet clocking and synchronization the clocking and synchronization portion of the qe1f- plus includes the receive clock configuration, transmit clock synchronization, and the slip buffers for each of the framers. the following table provides a summary of the rclkn clock operation in the receive direction (rclk1 above 2 mbit/s). note: control bit rxc (bit 5) in the framer clock control register x02h configures rclkn as an input or out- put for each of the framers. in the 8 mbit/s and 16 mbit/s transmission modes, the 2 mbit/s mvip mode, the 8 mbit/s h-mvip/h.100 mode and the 16 mbit/s pcm highway mode, the system clock must be an input. in the transmit direction, the system clock tclkn and sync pulse tsyncn are always inputs to the qe1f- plus . the transmit data tdatan is clocked out of the slip buffer by either the transmit system clock (tclkn), the local oscillator input (lo), or the recovered receive clock (lrclkn). the clock selection for each framer is controlled by txc1 (bit 7), and txc0 (bit 6) in framer clock control register x02h. the local oscillator input (lo) has a nominal frequency of 2.048 mhz. the following table provides a summary of the tclkn clock operation in the transmit direction (tclk1 above 2 mbit/s). clock reference for system applications that require the recovered receive clock, the qe1f- plus can provide two reference clocks derived from any of the four clock inputs (lrclkn), when enabled. the recovered receive clock input lrclkn that is used to derive the reference clock clkref1 (pin 46) is determined by the value written to con- interface mode clock rate sync edge in data/sig edge out comments 2 mbit/s trans. 2.048 mhz pos. neg. clock and sync pulse may be outputs. the rclkn clock is derived from the recovered received clock (lrclkn). see note. 8 mbit/s trans. 16.384 mhz pos. neg. system clock and sync pulse must be inputs. 16 mbit/s trans. 16.384 mhz pos. neg. system clock and sync pulse must be inputs. signaling highway is not used. 2 mbit/s mvip 2.048 mhz pos. pos. system clock and sync pulse must be inputs. 8 mbit/s h-mvip/h.100 16.384 mhz pos. neg. system clock and sync pulse must be inputs. 16 mbit/s pcm 16.384 mhz pos. neg. system clock and sync pulse must be inputs. signaling highway is not used. interface mode clock rate sync edge in data/sig edge in comments 2 mbit/s trans. 2.048 mhz pos. pos. 8 mbit/s trans. 16.384 mhz pos. pos. 16 mbit/s trans. 16.384 mhz pos. pos. signaling bus is not used. 2 mbit/s mvip 2.048 mhz pos. neg. 8 mbit/s h-mvip/h.100 16.384 mhz neg. pos. 16 mbit/s pcm 16.384 mhz pos. pos. signaling bus is not used. -101 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet trol bits cr1s1 and cr1s0 (bits 1 and 0) in the clock reference selection register (019h). the recovered receive clock that is used to derive the reference clock clkref2 (pin 2) is determined by the value written to control bits cr2s1 and cr2s0 (bits 7 and 6) in the clock reference selection register (019h). the following table lists the various conditions for enabling/disabling the clock reference signal on the clkref1 pin. the enref1 and 2048khz control bits are located at bits 3 and 4 in the clock reference selection register (019h). the lie control bit is located in the frame configuration register (x00h). the los alarm status bit (bit 7) is located in the e1 status register (x10h). note: x can be either state. the following table lists the various conditions for enabling/disabling the clock reference signal on the clkref2 pin. the enref2 and 2048khz control bits are located at bits 5 and 4 in the clock reference selection register (019h). the lie control bit (bit 1) is located in the frame configuration register (x00h). the los alarm status bit (bit 7) is located in the e1 status register (x10h). note: x can be either state. enref1 (control) los(n) (alarm) lie(n) (control) 2048khz (control) action 0xxx clkref1 pin tri-stated. 1 0 00 8 khz reference provided on clkref1. the 8 khz signal is derived from the recovered clock that is selected (lrclkn). 1 0 0 1 2048 khz reference provided on clkref1. the 2048 khz signal is derived from the recovered clock that is selected (lrclkn). 11xx clkref1 pin is forced low. 1x 1 x clkref1 pin is forced low when lintn is in the active true state. enref2 (control) los(n) (alarm) lie(n) (control) 2048khz (control) action 0xxx clkref2 pin tri-stated. 1 0 00 8 khz reference provided on clkref2. the 8 khz signal is derived from the recovered clock that is selected (lrclkn). 1 0 0 1 2048 khz reference provided on clkref2. the 2048 khz signal is derived from the recovered clock that is selected (lrclkn). 11xx clkref2 pin is forced low. 1x 1 x clkref2 pin is forced low when lintn is in the active true state -102 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet ais detection and generation both frame ais and time slot 16 ais are detected in the received e1 line signal. a line ais is detected when the received line signal has two or less zeros in each of two consecutive double-frame periods (512 bits). recovery occurs when each of two consecutive double-frame periods contains three or more zeros after frame alignment has been detected. the status of line ais is given by the lineais status bit (bit 0) in register x1bh. an ais in time slot 16 is detected when the received time slot has three or less zeros in each of two consecu- tive multiframe periods. recovery occurs when each of two consecutive multiframe periods contains four or more zeros or when the multiframe alignment signal has been detected. the status of time slot 16 ais is given by the ts16ais status bit (bit 1) in register x1bh. two enable bits are provided for or-gating the line ais and time slot 16 ais status bits together to provide unlatched and latched ais indications, and an interrupt when the associated mask bit is 0. control bit enlais (bit 0) in x1ah enables a line ais alarm. control bit e16ais (bit 1) in x1ah enables a received time slot 16 ais alarm. the qe1f- plus also provides control bits and enable bits for alarms to generate ais for the receive highway. when control bit stuais (bit 6) in register x07h is written with 1, the ais, oof and los alarms, if enabled by their respective enais (bit 2), enoof (bit 1), and enlos (bit 0) control bits in the signaling and time slot control register x03h, cause the generation of ais according to the following table. the table reflects the ais actions taken on out of frame (oof) alarm when enabled by enoof and stuais. control bits enais for ais and enlos for loss of signal function in the same manner. please note that the microprocessor can force ais to be generated for the receive data highway independent of the three control bits by writing a 1 to control bit sysall1 (bit 5) in register x07h. transmission modes (2 mbit/s, 8 mbit/s and 16 mbit/s) 2 mbit/s mvip mode, 8 mbit/s h-mvip/h.100 mode and 16 mbit/s pcm highway mode enoof stuais action 00 normal operation. no ais generated on signaling or data highway. 0 1 normal operation. no ais generated on signaling or data highway. 1 0 ais generated only on signaling highway when oof alarm is detected. a-bits are equal to 1. 11 ais generated on signaling and data highways when oof alarm is detected. a-bits on the signaling highway are equal to 1. enoof stuais action 00 normal operation. no ais generated on data highway. 0 1 normal operation. no ais generated on data highway. 1 0 normal operation. no ais generated on data highway when oof alarm is detected. 11 ais generated on data highway when oof alarm is detected. -103 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet in the transmit direction, from the transmit highway to the line, line ais and time slot 16 ais can be generated. when the microprocessor writes a 1 to control bit ais16 (bit 7) in register x07h, the all ones ais pattern is transmitted in time slot 16 continuously until the control bit is written with a 0. when the microprocessor writes a 1 to control bit aise (bit 1) in register x07h, the all ones ais pattern is transmitted in all the time slots of the frame continuously until the control bit is written with a 0. when the microprocessor writes a 1 to control bit ensais (bit 2) in register x00h, in the transmission modes only, the all ones ais pattern is transmitted in all time slots of the frame when the a-bits in the signaling highway are detected as ones. in addition, a status bit tuais (bit 3) in register x14h indicates when the a-bits are set to 1 in the transmission modes. the following table summarizes the various enable bits and actions for generating ais in the transmit direction. transmit ais generation hdlc channel a hdlc message frame is composed of four parts: an opening flag, the message (which consists of multiple bytes), a two-byte crc-16 frame check sequence, and a closing flag, as shown in figure 56 below. figure 56. hdlc format the opening and closing flags are represented by a single, unique 8-bit character defined as 01111110, which contains six contiguous ones. to avoid the occurrence of a false flag within the data stream, a zero is inserted (stuffed) after each string of five contiguous ones in the message or crc-16. reception of more than six con- tiguous ones is interpreted as a frame abort sequence. when an abort sequence is received, the remainder of the current frame is ignored and the received portion is discarded as an invalid frame. a two-byte crc-16 frame check sequence is computed across the contents of the message (after the opening flag), and appended to the end of the message. the time between consecutive frames is filled with one or more flags. when two or more flags occur in sequence, they may share the boundary zero between them (011111101111110). ensais ais16 aise action 000 normal operation. x x 1 ais generated. all ones inserted into all time slots. 0 1 0 ais generated for time slot 16. all ones inserted into time slot 16. 1xx ais generated when the a-bits in the transmit signaling highway are equal to ones in the transmission modes. all ones inserted into all time slots. bit 8 7654321 opening flag 0 1111110 message address and control information crc-16 closing flag 0 1111110 -104 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet a 16-byte fifo is provided in each direction for each framer, which permits short messages to be transmitted and received without having the microprocessor service the fifos during message reception. for long mes- sages, interrupts and status information are provided to facilitate fifo servicing by the microprocessor. for both short and long messages, the hdlc controller performs the following functions: - zero bit stuffing/destuffing (11111 to 111110 / 111110 to 11111) - itu-t crc-16 generation/checking (16-bit sequence) - flag generation/detection (01111110) - abort generation/detection (01111111...) - start of frame detection - end of frame detection - fifo overflow and underflow the bandwidth of the hdlc channel is determined by the spare bits in time slot 0. the five spare bits, labeled sa4-sa8, in bit positions 4-8 of time slot 0 in alternating (nfas) frames that do not carry the frame alignment sequence, each have a bandwidth of 4 kbit/s. any or all of the sa bits (sa4-sa8) can be programmed to build up the bandwidth of the hdlc channel from 4 kbit/s to 20 kbit/s. writing a 1 to an sa4-sa8 bit (bits 4-0) in hdlc link control register x0ch enables the corresponding sa bit to be used as part of the hdlc channel bandwidth for both the transmit and receive directions. the hdlc receiver is enabled when a 1 is written to control bit ehr (bit 7) in the hdlc link control register x08h. when enabled, the hdlc receiver will remove the stuffed zero bits, search for the opening flag and place the message contents in a 16-byte fifo. the hdlc controller will compute a crc and compare it against the crc that is received. the received crc is not stored in the fifo and is discarded after being received. the receive fifo is monitored for fill level, with maskable interrupts and latched indications provided. bits rxfs1 and rxfs0 (bits 3 and 2) in the hdlc link status register x16h indicate when the receive fifo is less than half full, equal to or greater than half full, full or overflowed. an interrupt may also be set at the end of the message, or when the fifo is half full, using the rhie control bit (bit 3) in the hdlc link control register x08h. thus, when the messages are always expected to be shorter than the maximum fifo depth of 16 bytes, the hdlc controller will generate an interrupt on the completion of the message. when the messages are expected to exceed the maximum fifo depth of 16 bytes, the controller will generate an interrupt when the fifo is half filled. bits c4-c0 (bits 4-0) in the hdlc link receive data register (x18h) provide the number of bytes presently stored in the receive fifo. bits rhis2-rhis0 (bits 7-5) in the hdlc link status register (x16h) provide mes- sage status and error indications. the hdlc controller will generate a maskable interrupt for start of message detected, valid message received, crc in error, and message aborted. the message bytes are read by the microprocessor at bits rhd7-rhd0 in register x17h for each framer. bit 0 corresponds to the first bit received in a byte. the hdlc transmitter is enabled when a 1 is written to control bit eht (bit 6) in the hdlc link control regis- ter x08h. when enabled, the hdlc controller will transmit flags until data is placed in the transmit fifo. up to 16 bytes can be placed in the 16-byte fifo. the message bytes are written into bits thd7-thd0 in the hdlc link transmit data register x0ah. bit 0 corresponds to the first bit transmitted. the transmit bytes are read from the transmit fifo and a 16-bit crc is computed until the end of message is detected. when the last byte of the message is written into the fifo, the microprocessor will set the end of message status bit eom (bit 4) in the hdlc link control register x08h. the computed 16-bit crc will be appended to the end of the mes- sage followed by at least one flag before another message is transmitted. when the transmit fifo is emptied without setting the eom bit, the fifo will set an underflow indication, and an abort character will be transmit- ted, thereby terminating the message. the transmit hdlc controller provides latched event bits and maskable interrupt bits related to the transmit fifo status. information such as underflow, overfill, and fill status is provided by reading status bits txfs1- txfs0 (bits 1-0) in the hdlc link status register x16h. -105 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet transmit hdlc fifo service interrupts may be programmed to occur when the transmit fifo is half empty, or when the last byte is sent, by setting control bit thie (bit 2) in register x08h. for short messages, the entire message may be written into the fifo, and the controller will generate an interrupt, indicated by status bit this (bit 4) in register x16h, when the message has been sent. for longer messages, the controller will gen- erate an interrupt when the fifo is ready to accept more data. there are four general types of message transfers, which are described below: transmitting long and short messages, and receiving long and short messages. the difference between the long and short messages is primarily in how the 16-bit fifos are serviced. with short messages, the entire message will fit into the fifos and interrupts will be generated when the end of the message occurs. with long messages, the message will not fit into the fifo, and the message will have to be transmitted or received in several segments. since long and short received messages are similar, their processing is described under the same heading. transmit short message to transmit a short message, first configure the transmitter to generate an interrupt at the end of message by writing a 0 to control bit thie (bit 2) in the hdlc link control register x08h. then write a 1 to control bit eht (bit 6) in register x08h to enable the transmitter. the hdlc controller will transmit flags until data is written into the transmit hdlc fifo. write the message into the transmit fifo by writing each byte in turn to thd7-thd0 in register x0ah. bit 0 represents the first bit in the byte to be transmitted. the bytes written into thd7-thd0 are transferred auto- matically into the fifo. after the last byte is written into the fifo, the eom (bit 4) in register x08h is written with a 1. the transmitter will then begin to send the message bytes until the fifo is empty. since the eom bit was set, the completion of the message will generate an interrupt, if not masked, indicated by the latched this status bit ethis, (bit 4) in x0eh. this latched status indication indicates that the message is complete or the fifo is half full. after the crc-16 is sent, the hdlc controller will start to send flags. transmit long message to transmit a long message, first configure the transmitter to generate an interrupt at the half full level of the fifo by writing a 1 to control bit thie (bit 2) in the hdlc link control register x08h. then write a 1 to control bit eht (bit 6) in register x08h to enable the transmitter. the hdlc controller will transmit flags until data is written into the transmit hdlc fifo. write the first 16-byte message segment into the transmit fifo by writing each byte in turn to thd7-thd0 in register x0ah. bit 0 represents the first bit in the byte to be transmitted. the bytes written into thd7-thd0 are transferred automatically into the fifo. the hdlc controller will then start to send the message bytes. when the fifo empties to the half full level, the ethis bit (bit 4) in register x0eh will be latched, and an interrupt generated, if the corresponding mask bit mthis (bit 4) in register x0fh is set to 0. this is an indication for the microprocessor to write another 8 bytes into the transmit hdlc fifo. this process of sending and refilling is repeated, 8 bytes at a time, until the last byte in the message is written into the fifo, when the eom (bit 4) in register x08h is written with a 1. the transmitter continues to send the final message bytes until the fifo is empty. when the last byte is transmitted and the fifo is empty, the ethis bit will latch while eom=1, indicat- ing completion of the message. after the crc-16 is sent, the hdlc controller will start to send flags. status bits txfs1-txfs0 (bits 1-0) in register x16h indicate the fill level of the transmit fifo. receive message to receive a message, first configure the receiver to generate an interrupt at the end of the message by writing a 0 to control bit rhie (bit 3) in the hdlc link control register x08h. enable interrupts from the fifo being half full by setting mask bits mrxfs1-mrxfs0 (bits 3-2) in control register x0fh to 00 and mask bits mrhis2- mrhis0 (bits 7-5) in control register x0fh to 001. finally, enable the receiver by writing a 1 to control bit ehr (bit 7) in register x08h. the receiver will generate an interrupt when the fifo is half full via status and event bits rxfs1-rxfs0 (bits -106 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet 3-2) in register x16h and erxfs1-erxfs0 (bits 3-2) in register x0eh or when an end of message is detected via status and event bits rhis2-rhis1 (bits 7-5) in register x16h and erhis2-erhis1 (bits 7-5) in the latched register x0eh. the receive message is read from the fifo by reading the bytes rhd7-rhd0 in register x17h. bit 0 represents the first bit in the byte to be received. the bytes in rhd7-rhd0 are transferred automatically from the receive fifo. when the interrupt occurs, the rhis2-rhis0 status bits (bits 7-5) in reg- ister x16h are also set in the erhis2-erhis0 bits (bits 7-5) in the latched register x0eh, indicating the mes- sage status. if the message in progress status is set, the microprocessor should read the message bytes from rhd7-rhd0 using the fifo depth bits c4-c0 in register x18h to detect the number of bytes stored in the receive fifo. please note that the fifo depth count is updated when the event indication is latched and inter- rupt generated, and will not be modified until it is read and cleared by the microprocessor. during long mes- sages, the count is allowed to change after the half full indication. if the microprocessor fails to read out the fifo in time, a second interrupt indication is generated. the reason for interrupt is indicated by status bits rxfs1-rxfs0 (bits 3-2) in register x16h. these control bits provide status information about the fill level of the receive fifo. an end of message is also indicated by the rhis2-rhis0 status bits. alarms the following line level alarms for each of the four framers are detected in the qe1f- plus : loss of signal (los), alarm indication signal (ais), out of frame (oof), remote alarm indication (rai), change of frame alignment (cfa), out of multiframe (oomf), transmit slip (txslip) and receive slip (rxslip). these alarms are provided by the e1 status and mask registers (registers x09h-x13h). in addition, the following hdlc link level alarms are supported by the qe1f- plus : receive hdlc event, transmit hdlc event, receive fifo event, transmit fifo event (registers x0eh, x0fh, x16h). each condition can cause an interrupt when the corresponding mask bit is set to 0. the latched status event indication (which can also be referred to as a software interrupt indication) for an alarm or condition is latched on either positive transitions, negative transitions, or both transitions. control bits rise (bit 6), and fall (bit 5) in the global configuration register 006h determine the transitions that cause an event bit to latch for all four framers, as shown in the following table: rise (bit 6) fall (bit 5) action 00 latched status bit indications in all registers disabled. hardware and software interrupt indications disabled. 1 0 latched status indication sets on positive alarm transition, along with generating a hardware interrupt provided the corresponding mask bit and the global interrupt bit gim (bit 7 in 006h) are both 0. 0 1 latched status indication sets on negative alarm transition, along with generating a hardware interrupt provided the corresponding mask bit and the global interrupt bit gim (bit 7 in 006h) are both 0. 11 latched status indication sets on both positive and negative alarm transitions, along with generating a hardware interrupt provided the corresponding mask bit and the global interrupt bit gim (bit 7 in 006h) are both 0. -107 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet the latched event is cleared by writing a 0 to the associated bit position in the latched status indication regis- ter. the qe1f- plus also provides a global interrupt mask (gim) bit for the microprocessor interrupt pin (pin 125, int/irq ). when a 1 is written to control bit gim (bit 7) in the global configuration register 006h, this hardware interrupt indication pin is tri-stated when a latched indication (event) bit is set. when a 0 is written into the gim bit, the hardware interrupt pin is enabled. when enabled, the polarity of the interrupt pin can be inverted by writing a 1 to control bit ipol (bit 4) in the global configuration register 006h. besides providing individual unlatched and latched alarm status indications, and interrupt mask bits, on a per framer basis, the qe1f- plus provides global interrupt status indication bits, as well as global interrupt mask bits and framer pointer bits in the global register segment (registers 00ah-00eh). an indication bit is set in register 00ah if the same type of alarm occurs in any of the four framers. registers 00ch and 00eh provide pointers to the framer which caused the line event or hdlc link event that triggered the interrupt. for example, assuming a loss of signal alarm occurred in framer 1 only, the los alarm will set the los bit (bit 7) in the unlatched register 110h. this alarm indication bit will be set to 1 for the duration of the alarm. assum- ing that control bits rise and fall (bits 6 and 5) in the global configuration register 006h are set to 10 (latched event set on a positive transition), the transition from 0 to 1 of the los alarm will cause the llos bit (bit 7) in register 111h to latch. a hardware interrupt will be generated on pin 125 if the interrupt mask bit mlos (bit 7) in register 109h is a 0, and the global interrupt mask bit gim (bit 7) in register 006h is a 0. if either of these bits is set to 1, the hardware interrupt will not occur. in addition, the latched los indication will also cause a global los indication (bit 7) in register 00ah. the framer in which the loss of signal alarm was detected can be found by reading bits 3-0 in register 00ch. the interrupt will be reset by first reading the llos latched alarm bit position (bit 7) in 111h and then writing a 0 into the bit position. this will also clear the global los indication bit. reading the register confirms that the loss of signal alarm occurred in framer 1. if the los alarm persists, it will not cause the latched bit position to relatch. the alarm status can be determined by now reading the unlatched status bit (bit 7) in register 110h, until it becomes 0, indicating that recovery has taken place. shadow registers the qe1f- plus also provides shadow registers for the alarms of each of the four framers. by applying a pulse at one second intervals to t1si (pin 40), an indication bit will be set in register x12h if the corresponding alarm occurred at any time in the last one second interval. in addition, an indication bit will be set in register x13h if the alarm is active, but the transition to the active state did not occur in the last one second interval (i.e., the alarm has persisted for longer than one second). the rising edge of the t1si pulse will also reset a latched event bit position in register x11h independent of the microprocessor. figure 57 illustrates the operation of the shadow registers for a loss of signal (los) alarm for framer 1. the behavior shown in the diagram also applies to the other line signal alarms in the same registers (ais, oof, rai, cfa, oomf, txslip, and rxslip). this figure assumes that control bits rise and fall (bits 6 and 5) in the global configuration register 006h are set to 10 (latched event set on a positive transition). please note that the los alarm causes a latched status indication llos (bit 7) in register 111h, and that the latched bit is reset by the rising edge of the t1si pulse. the plos status bit (bit 7) in register 112h is a 1 whenever there is a transition to los during the last one second interval or a los is present at the end of the last one-second interval. the flos status bit (bit 7) in register 113h is a 1 if the los alarm is active but did not become active during the previous one-second interval. -108 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet figure 57. shadow register operation in addition, shadow registers have been provided for monitoring the number of line errors that have occurred in one second intervals. when control bit enpmfm (bit 3 in global configuration register 006h) is set to a 1, the following shadow registers are updated with the count from the previous one-second interval on the rising edges of the one-second pulse provided at the t1si pin: a 10-bit register for a crc-4 count, a 16-bit register for coding violations, a 10-bit register for e-bit errors, and a 13-bit register for frame errors. the rising edge of the one-second pulse also clears the counters that were holding the count for the transfer to the shadow regis- ters. control bit enpmfm has no effect on the counters counting, just on the 1 second clearing. for example, the shadow registers for monitoring frame bit errors in framer 1 work in the following way. the 13-bit framing word error counter fbe12-fbe0 in registers 1fch and 1fdh counts the number of frame word errors over a one-second interval, which is determined by the t1si signal. at the rising edge of the pulse on the t1si pin, the count in registers 1fch and 1fdh is transferred to the shadow register lfbe12-lfbe0 in locations 1fah and 1fbh. the frame word error counter in registers 1fch and 1fdh is cleared at the same instant and it starts the error count for the next one-second interval. at the end of the next one-second interval, the shadow register is updated with the new count. a counter overflow bit fbeo is also provided (bit 7 in 1fdh), with a corresponding shadow overflow bit lfbeo (bit 7) in register 1fbh. the microprocessor can also clear the counter in registers 1fch and 1fdh by writing 00h to these registers. the shadow register holds its count during a microprocessor read cycle. t1si los llos plos flos t=0 sec t=1 sec t=2 sec t=3 sec t=4 sec t=5 sec t=6 sec (bit 7 in 113h) (bit 7 in 112h) (bit 7 in 111h) (bit 7 in 110h) (input on pin 40) 1. for this example, latched events are set only on positive event transitions. 2. plos = los + llos evaluated at one second boundaries (where ? + ? is a logical ? or ? ). 3. flos = los & llos evaluated at one second boundaries (where ? & ? is a logical ? and ? and x is a logical inversion). notes: -109 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet maintenance the qe1f- plus provides two loopback modes. local and remote line loopbacks are available for each of the four framers. in addition, a payload remote loopback is available. a per time slot loopback is also available in 2 mbit/s transmission and mvip modes when the system side clocks and frames are synchronous that loops any one or more received time slots and substitutes them for transmit time slots from the system side. these loopback modes allow the user to section a network path and isolate a specific failure. in addition, a pseudo- random test generator and analyzer are provided for board testing in 2 mbit/s transmission mode. local loopback local loopback for a framer is enabled when a 1 is written to control bit llp (bit 0) in register x05h. local loop- back connects the transmit path with the receive path (via the codec) in the direction toward the line, as illus- trated in figure 58 below. the loopback is independent of the line interface selected, nrz or dual unipolar (rail). when control bit tx1s (bit 2) in register x05h is written to 1, an ais (all ones signal) is transmitted in either nrz or rail mode to the line instead of data. please note that the normal transmit line ais can be enabled independently of the local loopback feature. when performing a local loopback, control bits rlp (bit 1) and payl (bit 3) in register x05h should be set to 0 to prevent errors in testing. figure 58. local loopback 0 1 hdb3 codec llp receive line 0 1 1 ? s transmit line line interface internal receive data internal transmit data note: bold/dashed lines show paths used for tx1s=1 and llp=1. (if rail=1) tx1s ami/ -110 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet remote line loopback remote line loopback for a framer is enabled when a 1 is written to control bit rlp (bit 1) in register x05h. remote line loopback connects the receive line data back to the transmitter, as illustrated in figure 59 below. the loopback is performed before the ami/hdb3 codec, allowing any coding violations to be passed through unaltered. the loopback is independent of the line interface selected, nrz or dual unipolar (rail). control bits payl (bit 3) and llp (bit 0) in register x05h should be set to 0 to prevent errors in testing. figure 59. remote line loopback payload remote loopback payload remote loopback for a framer is enabled when a 1 is written to control bit payl (bit 3) in register x05h. payload remote loopback connects the receive data back as the transmit data for time slots 1 through 31, as illustrated in figure 60 below. a small fifo provides for the delay necessary to allow the received time slot 0 to be skipped and the transmit time slot 0 to be inserted. time slot number and bit position within a time slot are not retained from receive to transmit, only the bit sequence is maintained. figure 60. payload remote loopback 1 0 rlp internal receive data internal transmit data transmit line receive line line interface note: bold/dashed lines show paths used for rlp=1. hdb3 codec (if rail=1) ami/ 0 1 payl transmit framer transmit line interface transmit line receive line line interface receive signaling receive data data & signaling highway transmit data transmit signaling note: bold/dashed lines show paths used for payl=1. receive framer receive line interface to rx slip buffer from tx slip buffer fifo -111 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet time slot remote loopback when control bit entslb (bit 4) in register 0ffh is set to 1, control bits tfts31 through tfts0 in registers x3ch through x3fh, if set to a 1, cause the framer to source the selected time slots from the receive data highway instead of tdatan pin. pins rclkn and rsyncn must be connected to pins tclkn and tsyncn respectively, and rclkn and rsyncn must be inputs (recovered receive clock cannot be selected) to prevent data errors in the looped back time slots. the loopback takes place after the slip buffer and is provided whether the receive slip buffer is enabled or disabled. control bits entslb and tfts31 through tfts0 are set to 0 upon a hardware reset. this function requires the presence of tclkn to operate correctly and is supported in transmission mode and 2 mbit/s mvip mode. figure 61 shows the basic operation of the time slot loopback feature. entslb when set to 1 over rides the transmit side gapped clock feature on pins tfe1gcn as selected by control bit fe1m (bit 0) in register x02h. though a loopback can be applied to time slot 0, the qe1f- plus regenerates time slot 0 and no change to the transmit framing pattern will occur. . figure 61. time slot remote loopback 0 1 to/from line interface receive framer receive signaling receive data entslb & (tfts0 + . . + tfts31) receive line interface rx tx transmit data transmit signaling time slot loopback disabled (entslb = 0) 0 1 to/from line interface receive framer receive signaling receive data entslb & (tfts0 + . . + tfts31) receive line interface rx tx transmit data transmit signaling time slot loopback enabled (entslb = 1) transmit framer transmit line interface transmit framer transmit line interface -112 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet boundary scan introduction the ieee 1149.1 standard defines the requirements of a boundary scan architecture that has been specified by the ieee joint test action group (jtag). boundary scan is a specialized scan architecture that provides observability and controllability for the interface pins of the device. the test access port block, which imple- ments the boundary scan functions, consists of a test access port (tap) controller, instruction and data regis- ters, and a boundary scan register path bordering the input and output pins, as illustrated in figure 62. the boundary scan test bus interface consists of four input signals (i.e., the test clock (tck), test mode select (tms), test data input (tdi) and test reset (trs ) input signals) and a test data output (tdo) output signal. the tap controller receives external control information via a test clock (tck) signal, a test mode select (tms) signal, and a test reset (trs ) signal, and it sends control signals to the internal scan paths. the scan path architecture consists of a two-bit serial instruction register and two or more serial data registers. the instruction and data registers are connected in parallel between the serial test data input (tdi) and test data output (tdo) signals. the test data input (tdi) signal is routed to both the instruction and data registers and is used to transfer serial data into a register during a scan operation. the test data output (tdo) is selected to send data from either register during a scan operation. when boundary scan testing is not being performed, the boundary scan register is transparent, allowing the input and output signals at the device pins to pass to and from the qe1f- plus device ? s internal logic, as illus- trated in figure 62. during boundary scan testing, the boundary scan register disables the normal flow of input and output signals to allow the device to be controlled and observed via scan operations. a timing diagram for the boundary scan feature is provided in figure 29. boundary scan support the maximum frequency the qe1f- plus device will support for boundary scan is 10 mhz. the qe1f- plus device performs the following boundary scan test instructions: - extest - sample/preload - bypass - idcode extest test instruction: one of the required boundary scan tests is the external boundary test (extest) instruction. when this instruc- tion is shifted in, the qe1f- plus device is forced into an off-line test mode. while in this test mode, the test bus can shift data through the boundary scan registers to control the external qe1f- plus input and output leads. sample/preload test instruction: when the sample/preload instruction is shifted in, the qe1f- plus device remains fully operational. while in this test mode, qe1f- plus input data, and data destined for device outputs, can be captured and shifted out for inspection. the data is captured in response to control signals sent to the tap controller. bypass test instruction: when the bypass instruction is shifted in, the qe1f- plus device remains fully operational. while in this test mode, a scan operation will transfer serial data from the tdi input, through an internal scan cell, to the tdo pin. the purpose of this instruction is to abbreviate the scan path through the circuits that are not being tested to only a single clock delay. idcode test instruction: the format of the idcode test instruction is "10". -113 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet boundary scan reset specific control of the trs pin is required in order to ensure that the boundary scan logic does not interfere with normal device operation. this pin must either be held low, asserted low, or asserted low then high (pulsed low), to asynchronously reset the test access port (tap) controller during power-on of the qe1f- plus . if boundary scan testing is to be performed and the pin is held low, then a pull-down resistor value should be chosen which will allow the tester to drive this pin high, but still meet the v il requirements listed in the input, output and i/o parameters section of this data sheet for worst case leakage currents of all devices sharing this pull-down resistor. figure 62. boundary scan schematic tap controller data registers instruction register tdi tdo in out boundary scan serial test data core logic of qe1f- plus boundary scan register signal input and output pins device trs tck tms control pins -114 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet boundary scan chain there are 139 scan cells in the qe1f- plus boundary scan chain. bidirectional signals require two scan cells. additional scan cells are used for direction control as needed. the following table shows the listed order of the scan cells and their function. a bsdl file is provided on the transwitch web site at www.transwitch.com. scan cell no. i/o pin no. symbol comments 138 control na xiotri_b a 1 enables the outputs of i/o type output3. 137 output3 39 rdata1_o39 136 output3 38 rsigl1_o38 135 control na xrxc1_b a 0 makes pins 37, 36 to be output. 134 bidir_in 37 rclk1_io37 133 bidir_out 37 rclk1_io37 132 bidir_in 36 rsync1_io36 131 bidir_out 36 rsync1_io36 130 input 35 tdata1_i35 129 control na xtsigl1_b a 0 makes pin 34 to be output. 128 bidir_in 34 tsigl1_io34 127 bidir_out 34 tsigl1_io34 126 input 33 tclk1_i33 125 input 32 tsync1_i32 124 output3 31 rdata2_o31 123 output3 29 rsigl2_o29 122 control na xrxc2_b a 0 makes pins 28, 27 to be output. 121 bidir_in 28 rclk2_io28 120 bidir_out 28 rclk2_io28 119 bidir_in 27 rsync2_io27 118 bidir_out 27 rsync2_io27 117 input 26 tdata2_i26 116 control na xtsigl2_b a 0 makes pin 24 to be output. 115 bidir_in 24 tsigl2_io24 114 bidir_out 24 tsigl2_io24 113 input 23 tclk2_i23 112 input 22 tsync2_i22 111 output3 21 rdata3_o21 110 output3 19 rsigl3_o19 109 control na xrxc3_b a 0 makes pins 18, 17 to be output. -115 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet 108 bidir_in 18 rclk3_io18 107 bidir_out 18 rclk3_io18 106 bidir_in 17 rsync3_io17 105 bidir_out 17 rsync3_io17 104 input 16 tdata3_i16 103 control na xtsigl3_b a 0 makes pin 15 to be output. 102 bidir_in 15 tsigl3_io15 101 bidir_out 15 tsigl3_io15 100 input 13 tclk3_i13 99 input 12 tsync3-i12 98 output3 11 rdata4_o11 97 output3 10 rsigl4_o10 96 control na xrdy_enb a 0 makes pin 9 to be output, 1 to be tri- stated. 95 output3 9 rdy_o9 94 control na xrxc4_b a 0 makes pins 8, 7 to be output. 93 bidir_in 8 rclk4_io8 92 bidir_out 8 rclk4_io8 91 bidir_in 7 rsync4_io7 90 bidir_out 7 rsync4_io7 89 input 6 tdata4_i6 88 control na xtsigl4_b a 0 makes pin 5 to be output. 87 bidir_in 5 tsigl4_io5 86 bidir_out 5 tsigl4_io5 85 input 4 tclk4_i4 84 input 3 tsync4_i3 83 control na xref_clk_en2_b a 0 makes pin 2 to be output enabled. 82 output3 2 clkref2_o2 81 input 1 reset _i1 80 input 128 w r _i128 79 input 127 se l _i127 78 input 126 r d _i126 77 output3 125 int_o125 76 control na xdt_en a 0 makes pins 123-114 to be output. scan cell no. i/o pin no. symbol comments -116 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet 75 bidir_in 123 dat7_io123 74 bidir_out 123 dat7_io123 73 bidir_in 122 dat6_io122 72 bidir_out 122 dat6_io122 71 bidir_in 120 dat5_io120 70 bidir_out 120 dat5_io120 69 bidir_in 119 dat4_io119 68 bidir_out 119 dat4_io119 67 bidir_in 118 dat3_io118 66 bidir_out 118 dat3_io118 65 bidir_in 117 dat2_io117 64 bidir_out 117 dat2_io117 63 bidir_in 115 dat1_io115 62 bidir_out 115 dat1_io115 61 bidir_in 114 dat0_io114 60 bidir_out 114 dat0_io114 59 input 113 addr11_i113 58 input 112 addr10_i112 57 input 110 addr9_i110 56 input 109 addr8_i109 55 input 108 addr7_i108 54 input 107 addr6_i107 53 input 106 addr5_i106 52 input 105 addr4_i105 51 input 104 addr3_i104 50 input 103 addr2_i103 49 input 102 addr1_i102 48 input 101 addr0_i101 47 input 100 sysclk_i100 46 input 99 moto_i99 45 output3 98 lcs4 _o98 44 output3 97 ltclk4_o97 43 output3 96 tneg4_o96 42 output3 95 tpos4_o95 scan cell no. i/o pin no. symbol comments -117 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet 41 input 93 lrclk4_i93 40 input 92 rneg4_i92 39 input 91 rpos4_i91 38 input 90 lint4_i90 37 output3 88 lcs3 _o88 36 output3 87 ltclk3_o87 35 output3 86 tneg3_o86 34 output3 85 tpos3_o85 33 input 83 lrclk3_i83 32 input 82 rneg3_i82 31 input 81 rpos3_i81 30 input 80 lint3_i80 29 output3 79 lcs2 _o79 28 output3 77 ltclk2_o77 27 output3 76 tneg2_o76 26 output3 75 tpos2_o75 25 input 74 lrclk2_i74 24 input 72 rneg2_i72 23 input 71 rpos2_i71 22 input 70 lint2_i70 21 output3 69 lcs1 _o69 20 output3 68 ltclk1_o68 19 output3 67 tneg1_o67 18 output3 66 tpos1_o66 17 input 65 lrclk1_i65 16 input 64 rneg1_i64 15 input 63 rpos1_i63 14 input 62 lint1_i62 13 control na xmon_enb a 0 enables pins 61, 60. 12 output3 61 lsclk_o61 11 output3 60 lsdo_o60 10 input 59 lsdi_i59 9 input 51 scan_enb_i51 8input50iotr i _i50 scan cell no. i/o pin no. symbol comments -118 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet reset procedure after power-up the qe1f- plus requires a hardware reset. this reset will reset all the per channel registers in the memory map below address x40h. it will also reset all of the global registers at addresses 004h through 0ffh. a low placed on the reset pin for at least 10 cycles of sysclk after all clocks become stable will accomplish the hardware reset. a global software reset is also available and should be applied at least 40 ms after power-up. this resets the internal state machines. it does not change the state of any of the control registers, performance counters and latched shadow registers. writing a 91h to control byte reset in register 005h places the qe1f- plus in a reset state. writing a value other than 91h to control byte reset will take the qe1f- plus out of the reset state. the reset register can be read to determine the reset state of the qe1f- plus . a value of 01h in the reset register indicates the qe1f- plus is in a reset state; a value of 00h indicates the qe1f- plus is not in reset. a per channel version of this function is available by writing a 1 to control bit srst (bit 7) in register x05h followed by writing a 0 to control bit srst. note that all the memory locations at addresses x40h through xffh are located in a per channel internal ram and are not reset by either a hardware reset or a soft- ware reset. changing the mode of operation of a framer should be followed by a per channel software reset (srst). the mode bits can be found in framer per channel registers x00h through x04h (rail, be, ensrai, lie, lpol, txcp, rxcp, txnrzp, rxnrzp, pwrd, fdat, fpol, bnal, txc1, txc0, rxc, tse, rse, tsr, rsr, typ1, typ0, rx_sig_inv, enais, enoof, enlos, oof1, oof0, bfaa, crca, casa, crcmd1, and crcmd0). not resetting the framer after changing most mode control bits will have minimal effect. if all 4 channels of the qe1f- plus are not implemented in an application, the channels that are not used should be powered down (control bit pwrd, bit 4 in register x01h is set to a 0) and all interrupts masked (register x09h set to ffh). 7 input 49 cso _i49 6 output3 48 prbsool_o48 5 control na xref_clk_en1_b a 0 enables pin 46. 4 output3 46 clkref1_o46 3 input 43 config1_i43 2 input 42 config2_i42 1 input 41 lo_i41 0 input 40 t1si_i40 scan cell no. i/o pin no. symbol comments -119 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet memory map the qe1f- plus memory map contains registers and counters which may be accessed by the microprocessor. addresses which are shown as spare, or are not listed in the memory map, must not be accessed by the microprocessor. the status designation r stands for a read-only unlatched register location, r(l) a read-only latched register location, w a write-only register location and rw a read/write register location. r and r(l) reg- ister bit positions designated as reserved (r) will read out an indeterminate value unless a 0 or 1 read value is indicated. rw reserved (r) bit positions must be set to 0 unless otherwise noted. common registers device id registers (see descriptions on page 128) customer notebook register (see descriptions on page 128) global software register (see descriptions on page 128) global configuration registers (see descriptions on page 129) address (hex) statusbit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 000r11010111 001r00010000 002r11000010 003 r revision level (currently 0000) 0 0 0 0 address (hex) statusbit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 004 rw customer defined byte address (hex) statusbit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 005 rw qe1f- plus chip reset (reset byte) address (hex) statusbit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 006 rw gim rise fall ipol enpmfm hmvip mtp16m enhwm 007 spare 008 spare 009 spare 01a rw losi7 - losi0 (loss of signal detection interval) 01b rw r (0) r (0) ond5 - ond0 (ones density loss of signal recovery interval) 01c-0fe spare 0ff rw wgdec r (0) r (0) entslb aags h100 r (0) r (0) -120 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet global status indication, interrupt mask and pointer registers (see descriptions on page 132) line interface control and monitoring registers (see descriptions on page 134) transmit and receive sync delay registers (see descriptions on page 136) clock reference selection register (see descriptions on page 136) address (hex) status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00a r glos gais goof grai gcfa goomf gtxslip grxslip 00b rw gmlos gmais gmoof gmrai gmcfa gmoomf gmtxslip gmrxslip 00c r reserved cha4 cha3 cha2 cha1 00d spare 00e r reserved chdl4 chdl3 chdl2 chdl1 00f spare address (hex) statusbit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 010 rw lcb7 - lcb0 (command byte) 011 rw ldo7 - ldo0 (line interface data output) 012 r ldi7 - ldi0 (line interface data input) 013 rw bdcst prbsfr prbsen esp/ emon rxtx r (0) e1chcs1 e1chcs0 014 rw reserved (set to 0) 015 rw reserved (set to 0) 016 rw reserved (set to 0) address (hex) statusbit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 017 rw tsd7 - tsd0 (transmit sync delay) 018 rw rsd7 - rsd0 (receive sync delay) address (hex) statusbit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 019 rw cr2s1 cr2s0 enref2 2048khz enref1 r (0) cr1s1 cr1s0 -121 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet per channel control and status indication registers the following registers configure, control or provide status information on a per channel basis. when an address location is written as xxxh, the first x indicates 1, 2, 3, or 4 to identify the associated channel, which corresponds to the like-numbered framer (n=1, 2, 3 or 4). framer configuration and control registers (see descriptions on page 138) software reset and loopback control register (see descriptions on page 146) system ais and test registers (see descriptions on page 147) address ch 1, 2, 3, 4 status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 100 200 300 400 rw rail be r (0) ensrai r (0) ensais lie lpol 101 201 301 401 rw txcp rxcp txnrzp pwrd fdat fpol bnal rxnrzp 102 202 302 402 rw txc1 txc0 rxc tse rse tsr rsr fe1m 103 203 303 403 rw typ1 typ0 rxf txf rx_sig_inv enais enoof enlos 104 204 304 404 rw oof1 oof0 bfaa casa crca crcmd1 crcmd0 rsyc 11a 21a 31a 41a rw auty autrai enraia enraiy eoocrc eoo16m e16ais enlais 138 238 338 438 rw rfts7 rfts6 rfts5 rfts4 rfts3 rfts2 rfts1 rfts0 139 239 339 439 rw rfts15 rfts14 rfts13 rfts12 rfts11 rfts10 rfts9 rfts8 13a 23a 33a 43a rw rfts23 rfts22 rfts21 rfts20 rfts19 rfts18 rfts17 rfts16 13b 23b 33b 43b rw rfts31 rfts30 rfts29 rfts28 rfts27 rfts26 rfts25 rfts24 13c 23c 33c 43c rw tfts7 tfts6 tfts5 tfts4 tfts3 tfts2 tfts1 tfts0 13d 23d 33d 43d rw tfts15 tfts14 tfts13 tfts12 tfts11 tfts10 tfts9 tfts8 13e 23e 33e 43e rw tfts23 tfts22 tfts21 tfts20 tfts19 tfts18 tfts17 tfts16 13f 23f 33f 43f rw tfts31 tfts30 tfts29 tfts28 tfts27 tfts26 tfts25 tfts24 address ch 1, 2, 3, 4 status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 105 205 305 405 rw srst reserved (set to 0) payl tx1s rlp llp address ch 1, 2, 3, 4 status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 106 206 306 406 rw reserved (set to 0) ts16ye nfase insprbs sfz rxfs txfs 107 207 307 407 rw ais16 stuais sysall1 crc fase raie aise bpv -122 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet e1 status and mask registers (see descriptions on page 149) counters and counter shadow registers (see descriptions on page 154) address ch 1, 2, 3, 4 status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 109 209 309 409 rw mlos mais moof mrai mcfa moomf mtxslip mrxslip 110 210 310 410 r los ais oof rai cfa oomf txslip rxslip 111 211 311 411 rw llos lais loof lrai lcfa loomf ltxslip lrxslip 112 212 312 412 rw plos pais poof prai pcfa poomf ptxslip prxslip 113 213 313 413 rw flos fais foof frai fcfa foomf ftxslip frxslip address ch 1, 2, 3, 4 status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1ec 2ec 3ec 4ec rw lebe7 - lebe0 (latched e-bit error counter shadow register, 10 bits) 1ed 2ed 3ed 4ed rw lebeo reserved (set to 0) lebe9 - lebe8 1ee 2ee 3ee 4ee rw ebe7 - ebe0 (e-bit error counter, 10 bits) 1ef 2ef 3ef 4ef rw ebeo reserved (set to 0) ebe9 - ebe8 1f0 2f0 3f0 4f0 rw lcrc7 - lcrc0 (latched crc-4 error counter shadow register, 10 bits) 1f1 2f1 3f1 4f1 rw lcrco reserved (set to 0) lcrc9 - lcrc8 1f2 2f2 3f2 4f2 rw crc7 - crc0 (crc-4 error counter, 10 bits) 1f3 2f3 3f3 4f3 rw crco reserved (set to 0) crc9 - crc8 1f4 2f4 3f4 4f4 rw lcv7 - lcv0 (latched coding violation counter shadow register, 16 bits) 1f5 2f5 3f5 4f5 rw lcv15 - lcv8 (latched coding violation counter shadow register, 16 bits) 1f6 2f6 3f6 4f6 rw lcvo reserved (set to 0) 1f7 2f7 3f7 4f7 rw cv7 - cv0 (coding violation counter, 16 bits) 1f8 2f8 3f8 4f8 rw cv15 - cv8 (coding violation counter, 16 bits) 1f9 2f9 3f9 4f9 rw cvo reserved (set to 0) 1fa 2fa 3fa 4fa rw lfbe7 - lfbe0 (latched framing word error counter shadow register, 13 bits) 1fb 2fb 3fb 4fb rw lfbeo reserved (set to 0) lfbe12-lfbe8 1fc 2fc 3fc 4fc rw fbe7 - fbe0 (framing word error counter, 13 bits) 1fd 2fd 3fd 4fd rw fbeo reserved (set to 0) fbe12-fbe8 1fe 2fe 3fe 4fe rw reserved (set to 0) 1ff 2ff 3ff 4ff rw reserved (set to 0) -123 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet operational status registers (see descriptions on page 158) slip buffer pointer status registers (see descriptions on page 160) receive time slot control registers (see descriptions on page 161) address ch 1, 2, 3, 4 status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 114 214 314 414 r txs1 txs0 rxs1 rxs0 tuais turai reserved 115 215 315 415 r rxsf txsf reserved lint 11b 21b 31b 41b r ncrc4 ecrce raia ts16me oocrcm oots16m ts16ais lineais address ch 1, 2, 3, 4 status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 120 220 320 420 rw twp7 - twp0 (transmit slip buffer write pointer) 121 221 321 421 rw trp7 - trp0 (transmit slip buffer read pointer) 122 222 322 422 rw twsbs reserved twpf3 - twpf0 (tx write pointer frame) 123 223 323 423 rw trsbs reserved trpf3 - trpf0 (tx read pointer frame) 124 224 324 424 rw rwp7 - rwp0 (receive slip buffer write pointer) 125 225 325 425 rw rrp7 - rrp0 (receive slip buffer read pointer) 126 226 326 426 rw rwsbs reserved rwpf3 - rwpf0 (rx write pointer frame) 127 227 327 427 rw rrsbs reserved rrpf3 - rrpf0 (rx read pointer frame) 128 228 328 428 rw reserved 129 229 329 429 rw reserved address ch 1, 2, 3, 4 status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 12a 22a 32a 42a rw rsis reserved (set to 0) rsa4s - rsa8s (rx national bit selection) 12b 22b 32b 42b rw reserved (set to 0) rx2s - rx0s 1e0 2e0 3e0 4e0 rw rde7 - rde1 (rx time slots 7-1 selection) r (0) 1e1 2e1 3e1 4e1 rw rde15 - rde8 (rx time slots 15-8 selection) 1e2 2e2 3e2 4e2 rw rde23 - rde16 (rx time slots 23-16 selection) 1e3 2e3 3e3 4e3 rw rde31 - rde24 (rx time slots 31-24 selection) -124 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet receive time slot registers (see descriptions on page 163) transmit time slot control registers (see descriptions on page 164) transmit time slot registers (see descriptions on page 166) address ch 1, 2, 3, 4 status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 140 240 340 440 rw rfas - receive frame alignment pattern fas (time slot 0 - frame 1) 141 - 15f ch 1 241 - 25f ch 2 341 - 35f ch 3 441 - 45f ch 4 rw frame 1 rts1-rts31 (receive time slots ts1 - ts31) x41 - time slot 1 x5f - time slot 31 160 260 360 460 rw rnfas - receive no frame alignment pattern nfas (time slot 0 - frame 2) 161 - 17f ch 1 261 - 27f ch 2 361 - 37f ch 3 461 - 47f ch 4 rw frame 2 rts1-rts31 (receive time slots ts1 - ts31) x61 - time slot 1 x7f - time slot 31 address ch 1, 2, 3, 4 status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 12c 22c 32c 42c rw tsis reserved tsa4s - tsa8s (tx national bit selection) 12d 22d 32d 42d rw reserved (set to 0) tx2s - tx0s 12e 22e 32e 42e rw reserved (set to 0) 12f 22f 32f 42f rw reserved (set to 0) 1e4 2e4 3e4 4e4 rw tde7 - tde1 (tx time slots 7-1 selection) r (0) 1e5 2e5 3e5 4e5 rw tde15 - tde8 (tx time slots 15-8 selection) 1e6 2e6 3e6 4e6 rw tde23 - tde16 (tx time slots 23-16 selection) 1e7 2e7 3e7 4e7 rw tde31 - tde24 (tx time slots 31-24 selection) address ch 1, 2, 3, 4 status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 190 290 390 490 rw tfas - transmit frame alignment pattern fas (time slot 0 - frame 1) 191 - 1af ch 1 291 - 2af ch 2 391 - 3af ch 3 491 - 4af ch 4 rw frame 1 tts1-tts31 (transmit time slots ts1 - ts31) x91 - time slot 1 xaf - time slot 31 1b0 2b0 3b0 4b0 rw tnfas - transmit no frame alignment pattern nfas (time slot 0 - frame 2) 1b1 - 1cf ch 1 2b1 - 2cf ch 2 3b1 - 3cf ch 3 4b1 - 4cf ch 4 rw frame 2 tts1-tts31 (transmit time slots ts1 - ts31) xb1 - time slot 1 xcf - time slot 31 -125 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet signaling control registers (see descriptions on page 167 ) receive and transmit signaling registers ( see descriptions on page 168 ) hdlc link control registers ( see descriptions on page 176 ) hdlc link transmit and receive data registers ( see descriptions on page 177 ) address ch 1, 2, 3, 4 status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1e8 2e8 3e8 4e8 rw se8 - se1 (signaling enable for channels 8-1 selection) 1e9 2e9 3e9 4e9 rw se16 - se9 (signaling enable for channels 16-9 selection) 1ea 2ea 3ea 4ea rw se24 - se17 (signaling enable for channels 24-17 selection) 1eb 2eb 3eb 4eb rw reserved se30 - se25 (signaling enable for channels 30-25 selection) address ch 1, 2, 3, 4 status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 180 280 380 480 rw receive multiframe pattern rsigmas (0000) rx0 ry rx1 rx2 181 - 18f ch 1 281 - 28f ch 2 381 - 38f ch 3 481 - 48f ch 4 rw receive signaling bits ra1-rd1 (a1 b1 c1 d1) to ra15-rd15 (a15 b15 c15 d15) receive signaling bits ra16-rd16 (a16 b16 c16 d16) to ra30-rd30 (a30 b30 c30 d30) 1d0 2d0 3d0 4d0 rw transmit multiframe pattern tsigmas (0000) tx0 ty tx1 tx2 1d1 - 1df ch 1 2d1 - 2df ch 2 3d1 - 3df ch 3 4d1 - 4df ch 4 rw transmit signaling bits ta1-td1 (a1 b1 c1 d1) to ta15-td15 (a15 b15 c15 d15) transmit signaling bits ta16-td16 (a16 b16 c16 d16) to ta30-td30 (a30 b30 c30 d30) address ch 1, 2, 3, 4 status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 108 208 308 408 rw ehr eht tab eom rhie thie reserved 10b 20b 30b 40b rw reserved (set to 0) 10c 20c 30c 40c rw reserved (set to 0) sa4 sa5 sa6 sa7 sa8 address ch 1, 2, 3, 4 status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 10a 20a 30a 40a w thd7-thd0 (hdlc transmit data) 117 217 317 417 r rhd7-rhd0 (hdlc receive data) 118 218 318 418 rw reserved (set to 0) c4 - c0 (hdlc receive fifo depth) -126 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet hdlc link status registers (see descriptions on page 178) spare registers the following registers are designated as spare. they must not be accessed for read or write operations by the microprocessor. 007h, 008h, 009h, 00dh, 00fh, 01ch to 0feh, x0dh, x1ch and x1dh. reserved registers the following read/write registers and bit locations in read/write registers are designated as reserved and require zeros to be written into them. some of these bits are designated as internal test bits, etc. global registers per framer registers (x = 1, 2, 3, 4) address ch 1, 2, 3, 4 status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 10e 20e 30e 40e rw erhis2 - erhis0 ethis erxfs1 - erxfs0 etxfs1 - etxfs0 10f 20f 30f 40f rw mrhis2 - mrhis0 mthis mrxfs1 - mrxfs0 mtxfs1 - mtxfs0 116 216 316 416 r rhis2 - rhis0 this rxfs1 - rxfs0 txfs1 - txfs0 119 219 319 419 rw reserved (set to 0) register bits comments 013 2 write a 0 to this bit location 014 7 - 0 write a 0 to these bit locations 015 7 - 0 write a 0 to these bit locations 016 7 - 0 write a 0 to these bit locations 019 2 write a 0 to this bit location 01b 7, 6 write a 0 to these bit locations 0ff 6, 5 write a 0 to these bit locations 0ff 1, 0 write a 0 to these bit locations register bits comments x00 5, 3 write a 0 to these bit locations x05 6 - 4 write a 0 to these bit locations x06 7, 6 write a 0 to these bit locations x08 1, 0 write a 0 to these bit locations x0b 7 - 0 write a 0 to these bit locations x0c 7 - 5 write a 0 to these bit locations -127 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet x18 7 - 5 write a 0 to these bit locations x19 7 - 0 write a 0 to these bit locations x2a 6, 5 write a 0 to these bit locations x2b 7 - 3 write a 0 to these bit locations x2c 6, 5 write a 0 to these bit locations x2d 7 - 3 write a 0 to these bit locations x2e 7 - 0 write a 0 to these bit locations x2f 7 - 0 write a 0 to these bit locations xe0 0 write a 0 to this bit location xe4 0 write a 0 to this bit location xeb 7, 6 write a 0 to these bit locations xed 6 - 2 write a 0 to these bit locations xef 6 - 2 write a 0 to these bit locations xf1 6 - 2 write a 0 to these bit locations xf3 6 - 2 write a 0 to these bit locations xf6 6 - 0 write a 0 to these bit locations xf9 6 - 0 write a 0 to these bit locations xfb 6 - 5 write a 0 to these bit locations xfd 6 - 5 write a 0 to these bit locations xfe 7 - 0 write a 0 to these bit locations xff 7 - 0 write a 0 to these bit locations register bits comments -128 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet memory map descriptions common registers device id registers the manufacturer id, part number and version of the qe1f- plus are implemented in registers 000h - 003h with read-only capability. the manufacturer id is 107 (decimal), and has been assigned for transwitch by the joint electron device engineering council (jedec) of the solid state products engineering council. this field is 12 bits in length (06bh), and is assigned to bits 3 through 0 in register 001h, and bits 7 through 1 (lsb) in register 000h and a fixed 1 bit in bit 0 of register 000h, (i.e., 0000 11010111 or 0d7h.), as shown above in the memory map section. the part number is 16 bits long. the internal part number for the qe1f- plus is 03105 (decimal). the binary value (0c21h) is assigned to bits 3-0 in register 003h, bits 7-0 in register 002h, and bits 7-4 (lsb) in register 001h. the revision level in bits 7-4 of register 003h represents the version number of the device and will vary as the device evolves. the current value is 0h. customer notebook register the read/write bits in this register location are provided for use by the customer ? s application software. global software register the control bits in this read/write register location are used for resetting the qe1f- plus . address bit symbol description 004 7-0 notebook user defined register: the bits in this read/write register are provided for use by the application software. the contents of this register will have no direct effect on the operation of the qe1f- plus . address bit symbol description 005 7-0 reset software reset: writing a 91h into this location will reset the qe1f- plus . writing a value other than 91h will remove the qe1f- plus from the reset state. reading this location provides a value of 00h if the qe1f- plus is not in reset, and 01h if the qe1f- plus is reset. the qe1f- plus defaults to reset deactivation on an external hardware reset (e.g., power-up). at least 40 ms after power-up, a software reset should be applied to this register location in order to clear the qe1f- plus prior to programming the register positions. the software reset resets the internal state machines. the control registers, performance counters and the latched/shadow registers are not affected by this reset. in addi- tion to this global reset byte, each of the four framers has an individual software reset bit, which is assigned to bit 7 (srst) in register location x05h (where x corresponds to the framer ? s number, n). -129 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet global configuration registers the bits in these read/write registers control qe1f- plus operations on a global basis for all four framers. address bit symbol description 006 7 gim global interrupt mask bit: a 1 disables (masks) the hardware interrupt pin (pin 125). when not masked (0), any latched status event (if not masked by the corresponding event mask bit) causes a hardware inter- rupt to occur. 6rise rising edge latched status event bits enable: this bit works in con- junction with the fall control bit (bit 5) to provide the following states for controlling the setting of the latched status event indication bits for the four framers. rise fal l action 0 0 latched status bit indications for all framers dis- abled. hardware interrupt indication disabled. 0 1 latched status indication bits for all framers set on a negative status event bit indication transi- tion. 1 0 latched status indication bits for all framers set on a positive status event bit indication transition. 1 1 latched status indication bits for all framers set on both a positive and a negative status event bit indication transition. 5fall falling edge latched status event bits enable: works in conjunction with the rise control bit according to the table given above. 4ipol hardware interrupt polarity sense: when set to 1, the polarity of the hardware interrupt pin (pin 125) is inverted from active high to active low for the intel microprocessor bus. when the motorola microprocessor bus is selected, the polarity of the hardware interrupt pin (pin 125) is inverted from active low to active high. 3enpmfm enable performance monitoring and fault monitoring feature: when set to 1, the monitoring feature for the shadow registers (x12h and x13h) and latched counters (xech, xedh, xf0h, xf1h, xf4h, xf5h, xf6h, xfah, and xfbh) is enabled. the register bits set on the rising edges of the one second pulse, which must be present on the t1si pin (pin 40). when set to 0, the monitoring feature is disabled. 2hmvip multi-vendor integration protocol: this control bit works in conjunc- tion with the mtp16m control bit (bit 1) and the config1 lead (pin 43) to provide the following system highway modes of operation. config 1 hmvip mtp16m s ystem interface low 0 0 2 mbit/s transmission mode low 1 0 8 mbit/s transmission mode low 0 1 16 mbit/s transmission mode high 0 0 2 mbit/s mvip mode high 1 0 8 mbit/s h-mvip/h.100 mode high 0 1 16 mbit/s pcm highway mode x 1 1 not valid, do not use -130 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet 006 (cont.) 1mtp16m multiplexed 16 mbit/s format: this control bit works in conjunction with the hmvip control bit (bit 2) and the config1 lead (pin 43) to pro- vide the system highway modes of operation, as listed in the table above. 0enhwm enable hardware mask hierarchy: when this bit is set to 1, the mask- ing hierarchy for the alarms is enabled according to the table below: 01a 7-0 losi7-losi0 loss of signal detection and recovery interval select: the binary value written to this register selects the number of consecutive missing pulses used to declare loss of signal. the normal range is between 10 and 255. bit 0 is the lsb. this value is also used to set the duration of the recovery interval (see register 01bh). 01b 7-6 reserved reserved: set to 0. 5-0 ond5-ond0 ones density loss of signal recovery threshold select: the binary value written to this register selects the minimum number of ones that must occur in the recovery interval set up by register 01ah to recover loss of signal. this value must be less than the value written in register 01ah. for a loss of signal recovery interval value of 255, the recovery threshold value is normally set to 32. bit 0 is the lsb. 0ff 7 wgdec test equipment bpv selection: a 1 enables the decoder to detect coding violations as found in certain test equipment (e.g., wandel & gol- terman ? ). a 0 enables the decoder to detect coding violations as found in other types of test equipment (e.g., tberd ? ). the following table summarizes the two decoding procedures of coding violations: 6-5 reserved reserved: set to 0. 4entslb enable time slot loopback feature: a 1 enables the time slot loop- back feature for the four framers. time slot loopbacks occur when the corresponding control bits tfts31-tfts0 are written with a 1. pins rclkn and rsyncn must be connected to pins tclkn and tsyncn respectively to prevent data errors in the looped back time slots. address bit symbol description alarm suppression table (shaded columns indicate suppressed alarms) direction los line ais oof rai crc oomf ts16 oomf ts16 ais slips line port to system x x x bpv hdb3 1 (w & g) 0 (tberd) + + or - - 000 (preceding bit changed) 11 0bv or 000v 0000 1010 or 0001 bb00v after odd 1000 1101 bb00v after even 1000 1001 -131 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet 0ff (cont.) 3aags alternative alarm generation selection: when set to a 1, a-bit and e-bit alarm generation with respect to out of frame and out of multiframe behave as specified in ets 300 011 (also see itu-t g.704, g.706, 1988). a bit (rai) will be set to a 1 for at least one nfas frame pattern each time a search for multiframe alignment is performed (which is every 8 ms until multiframe alignment is achieved). e-bits will be set to 1 unless crc-4 errors are detected after multiframe alignment is achieved. note: crca must be set to 1 for normal operation. see control bit crca description (bit 3 in register x04h) for operation when crca is set to 1. one e-bit may be set to 0 immediately after the qe1f- plus frames up, even though the first crc-4 is correct. when set to a 0, a-bit and e-bit alarm generation with respect to out of frame and out of multiframe should behave as specified in itu-t g.704, g.706, 1991. in this case the e-bits are set to 0 and the a-bit is set to 1 initially. when basic frame alignment is reached the a-bit is set to 0. the a-bit is only set to 1 again if basic frame alignment is lost due to loss of the time slot 0 fas and nfas codes or excessive crc-4 errors after multiframe alignment is reached (not if an alternate frame position is chosen or if multiframe alignment can not be reached). the e-bits are set to 1 once multiframe alignment is reached, one e-bit toggling to 0 for each sub-multiframe error detected in a multiframe using the crc-4 check. 2h100 h.100/h-mvip selection: a 1 enables the h.100 synchronization pulse option when config1 (pin 43) is high, and control bits hmvip and mtp16m are set to 10 respectively (bits 2 and 1 of register 006h). in this mode the nominal pulse widths of rsync1 and tsync1 are two clock periods of rclk1 and tclk1 respectively. the active low rsync1 and tsync1 signals straddle the transition between bit 8 of time slot 31 of framer number 4 and bit 1 of time slot 0 of framer num- ber 1. a 0 enables the h-mvip synchronization pulse option when config1 (pin 43) is high, and control bits hmvip and mtp16m are set to 10 respectively (bits 2 and 1 of register 006h). in this mode the nominal pulse widths of rsync1 and tsync1 are four clock periods of rclk1 and tclk1 respectively. the active low rsync1 and tsync1 signals straddle bit 8 of time slot 31 of framer number 4 and bit 1 of time slot 0 of framer number 1. 1-0 reserved reserved: set to 0. address bit symbol description -132 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet global status indication, mask and pointer registers these registers are read-only, except for the mask register 00bh, which is read/write. the bits in the global status indication register 00ah indicate an alarm caused by a line event on a global basis (i.e., in any framer). if the corresponding mask bit is written with a 1 in the e1 mask register (x09h) it prevents an interrupt gener- ation, but the global indication will be present in register 00ah. each event bit is formed by or-gating the corre- sponding event bits in each of the four framer channels (registers x10h) to provide the individual status indication in register 00ah. a 1 written into a bit position in the global mask register 00bh will mask the inter- rupt indication for the corresponding bit position in register 00ah. the bits in register locations 00ch and 00eh provide a pointer to the framer which caused the line or hdlc link latched event. global status indication register address bit symbol description 00a 7 glos global loss of signal (los) indication: this bit is a 1 when any of the four framer channels has detected a loss of signal alarm. 6gais global ais indication: this bit is a 1 when any of the four framer chan- nels has detected an ais alarm. 5goof global out of frame (oof) indication: this bit is a 1 when any of the four framer channels has detected an out of frame alarm. 4grai global remote alarm indication (rai): this bit is a 1 when any of the four framers has detected an rai alarm. 3gcfa global change in frame alignment (cfa) indication: this bit is a 1 when any of the four framer channels has detected a change in frame alignment. 2 goomf global out of multiframe alignment (oomf) indication: this bit is a 1 when any of the framer channels has detected an out of multiframe alignment alarm. 1gtxslip global transmit slip indication: this bit is a 1 when any of the four framer channels has detected a transmit slip. 0grxslip global receive slip indication: this bit is a 1 when any of the four framer channels has detected a receive slip. -133 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet global interrupt mask register global pointer registers address bit symbol description 00b 7 gmlos global loss of signal (los) mask bit: when set to 1, a loss of signal alarm detected in any framer channel (llos, registers x11h) is masked from providing an interrupt indication. 6gmais global ais mask bit: when set to 1, an ais condition detected in any framer channel (lais, registers x11h) is masked from providing an interrupt indication. 5gmoof global out of frame (oof) mask bit: when set to 1, an out of frame alarm detected in any framer channel (loof, registers x11h) is masked from providing an interrupt indication. 4gmrai global remote alarm indication (rai) mask bit: when set to 1, an rai in any framer channel (lrai, registers x11h) is masked from pro- viding an interrupt indication. 3gmcfa global change in frame alignment (cfa) mask bit: when set to 1, a change in frame alignment indication in any framer channel (lcfa, reg- isters x11h) is masked from providing an interrupt indication. 2gmoomf global out of multiframe alignment (oomf) mask bit: when set to 1, an out of multiframe alarm detected in any framer channel (loomf, registers x11h) is masked from providing an interrupt indication. 1 gmtxslip global transmit slip indication mask bit: when set to 1, a transmit slip detected in any framer channel (ltxslip, registers x11h) is masked from providing an interrupt indication. 0 gmrxslip global receive slip indication mask bit: when set to 1, a receive slip detected in any framer channel (lrxslip, registers x11h) is masked from providing an interrupt indication. address bit symbol description 00c 7-4 reserved reserved: disregard these bits. 3-0 cha4-cha1 channel activity line events for channels 4-1: a 1 in a bit position points to (indicates) the framer channel that caused the global status indication because of a line event (e.g., loss of signal). for example, 0011 indicates that channels 2 and 1 have a latched line event. 00e 7-4 reserved reserved : disregard these bits. 3-0 chdl4-chdl1 channel activity hdlc link event for channels 4-1: a 1 in a bit position points to (indicates) the framer channel that caused the global status indication because of a hdlc link event (e.g., receive fifo event). for example, 1000 indicates that channel 4 has a latched data link event. -134 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet line interface control and monitoring registers these registers are read/write, except for register 012h, which is read-only unlatched. the control bits in these registers determine the line interface control information flow between the qe1f- plus and the external line interface transceivers, enable the pseudo-random generator and analyzer, and enable the monitor mode for the qe1f- plus . the line interface control feature is enabled by placing a low on the config2 pin (pin 42). address bit symbol description 010 7-0 lcb7-lcb0 line interface control command byte: the bits in this register con- tain the command byte for the external line interface transceiver. the contents of the command byte written into this location depend on the transceiver selected. please consult the transceiver data sheet for the appropriate codes. the command byte is transmitted via the line inter- face control serial port output (lsdo). this byte is shifted out of this register starting with bit lcb0 first, and represents the first byte trans- mitted on the lsdo pin (pin 60). 011 7-0 ldo7-ldo0 line interface control serial data output byte: the bits in this regis- ter contain the data byte which is written to the selected external line interface transceiver. the data byte is transmitted via the line interface control serial port output (lsdo). this byte is shifted out of this register starting with bit ldo0 first, and represents the second byte transmitted on the lsdo pin. 012 7-0 ldi7-ldi0 line interface control serial data input byte: the bits in this register contain the data byte which is read from the selected external line inter- face transceiver. the data byte is received via the line interface control serial port input (lsdi). this byte is shifted into this register starting with bit ldi0 first. 013 7 bdcst broadcast command: when this bit is set to 1, the two bytes in the line interface control command and serial data output byte registers are broadcasted to all external line interface transceivers. this is accomplished by forcing all line interface chip select signals (lcsn ) active low. this feature is disabled in the internal e1 monitor mode (config2 pin is low). 6prbsfr prbs framed mode : when this bit is set to 1, the internal 2 15 -1 prbs generator and analyzer are configured to operate in the framed mode, which means that the channel ? s transmit framer block generates fram- ing. when set to 0 for unframed mode, the internal 2 15 -1 prbs genera- tor and analyzer are configured to operate on all of the bits in the transmit and receive data highways. both the framer and the prbs gen- erator and analyzer must be set to the same mode. if prbsfr = 1, then crcmd1-crcmd0 00 (bits 2-1 in register x04h). if prbsfr = 0, then crcmd1-crcmd0 = 00. -135 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet 013 (cont.) 5prbsen prbs enable: when this bit is set to 1, the internal 2 15 -1 prbs ana- lyzer is enabled in the 2 mbit/s transmission mode only. the e1 chan- nel selection bits (bits 1 and 0) in this register select which channel's receive data highway is connected to the analyzer. the state of the ana- lyzer is provided on pin prbsool. a low on this pin indicates that the analyzer is locked, while a high indicates the unlocked state. the recov- ered line clock is the clock source for the analyzer. if the receive slip buffer is enabled, its read clock source is the lrclkn input pin. the lo input pin is the clock source for the generator. if the transmit slip buffer is enabled, then the input lo must be synchronous and in phase with tclkn. 4esp/emon enable serial port: this feature is enabled when a low is placed on the config2 pin. when set to 1, a single transfer takes place between the external line interface transceiver and its associated qe1f- plus framer via the line interface control serial port. the external transceiver is accessed by an active low chip select signal (lcsn ) for the transceiver selected by the e1 selection bits, bits 1 and 0 in this register. this bit must be first set to 0 and then to 1 before another transfer is enabled. enable monitor port: when the internal e1 monitor mode is selected by placing a high on the config2 pin, a 1 enables the nrz data stream via the monclk and mondto pins. a 0 causes the monclk and mondto pins to be tri-stated. 3rxtx rx or tx monitor selection: when the internal e1 monitor mode is selected (a high is placed on the config2 pin), a 0 enables the trans- mit side to be monitored. a 1 enables the receive side to be monitored. 2 reserved reserved: set to 0. 1-0 e1chcs1- e1chcs0 e1 channel selection: selects the external line interface transceiver, the internal e1 channel (framer) for monitoring and the receive data highway channel for the internal 2 15 -1 prbs analyzer, according to the table given below: bit 1 bit 0 transceiver/e1 monitored/analyzer 0 0 channel 1 0 1 channel 2 1 0 channel 3 1 1 channel 4 address bit symbol description -136 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet transmit and receive sync delay registers the value written in register 017h controls the number of clock cycles the transmit sync pulse (tsyncn) will be delayed relative to the transmit system clock (tclkn). the value written in register 018h controls the num- ber of clock cycles the receive system sync pulse (rsyncn) will be delayed relative to the receive system clock (rclkn), when rsyncn and rclkn are set to be inputs (rxc=0). clock reference selection register the control bits in this read/write register are used to control the clock references for the qe1f- plus . address bit symbol description 017 7-0 tsd7-tsd0 transmit sync delay: the value written into this register location spec- ifies the number of transmit clock cycles (tclkn) that the transmit sync signal (tsyncn) is delayed internal to the qe1f- plus . if no delay is required then 00 hex must be written into this register. for h-mvip/ h.100, 8 mbit/s and 16 mbit/s transmission, and 16 mbit/s pcm highway modes, the number of clock cycles delay is obtained by multiplying this value by 8. 018 7-0 rsd7-rsd0 receive sync delay: the value written into this register location speci- fies the number of receive clock cycles (rclkn) that the receive sync signal (rsyncn) is delayed internal to the qe1f- plus . if no delay is required then 00 hex must be written into this register. for h-mvip/ h.100, 8 mbit/s and 16 mbit/s transmission, and 16 mbit/s pcm highway modes, the number of clock cycles delay is obtained by multiplying this value by 8. address bit symbol description 019 7-6 cr2s1- cr2s0 reference channel clock 2 selection: selects the channel from which the reference clock clkref2 (pin 2) is derived, according to the table given below: b i t 7 b i t 6 r eference clock derived fro m 0 0 channel 1 0 1 channel 2 1 0 channel 3 1 1 channel 4 5 enref2 enable reference clock 2: when set to 1, the reference clock on clkref2 (pin 2) is enabled. the reference clock is selected by the ref- erence channel clock 2 selection control bits (bits 7 and 6), and is derived from receive clock (lrclkn) for the selected channel. when set to 0, clkref2 (pin 2) is tri-stated. note: when set to 1, clkref2 will be forced low when a loss of signal is detected either locally (los), or from the external line interface trans- ceiver when control bit lie in framer configuration register x00h is a 1. 42048khz 2048 khz reference clock enable: when set to one, the 2048 khz reference clock selected by the reference channel clock 2 selection control bits is provided on the pins clkref2 and/or clkref1, when enabled. when set to zero, a divide by 256 circuit is placed between the receive line clock (lrclkn) and pins clkref2 and/or clkref1, when enabled. the output will be 8 khz reference signals. -137 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet 019 (cont.) 3 enref1 enable reference clock 1: when set to 1, the reference clock on clkref1 (pin 46) is enabled. the reference clock is selected by the reference channel clock 1 selection control bits (bits 1 and 0), and is derived from receive clock (lrclkn) for the selected channel. when set to 0, clkref1 (pin 46) is tri-stated. note: when set to 1, clkref1 will be forced low when a loss of signal is detected either locally (los), or from the external line interface trans- ceiver when control bit lie in bit 1 of framer configuration register x00h is a 1. 2 reserved reserved: set to 0. 1-0 cr1s1- cr1s0 reference channel clock 1 selection: selects the channel from which the reference clock clkref1 (pin 46) is derived, according to the table given below: bit 1 bit 0 reference clock derived fro m 0 0 channel 1 0 1 channel 2 1 0 channel 3 1 1 channel 4 address bit symbol description -138 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet per channel control and status indication registers framer configuration and control registers the control bits in the following read/write registers are used to configure the qe1f- plus for the various modes of operation on a per channel basis. in the following table, n indicates the channel (framer) number 1-4. address bit symbol description 100 - ch 1 200 - ch 2 300 - ch 3 400 - ch 4 7rail dual unipolar/nrz mode selection: when set to 1, the line interface for channel n is configured to operate in the dual unipolar mode (rail interface). when set to 0, the line interface for channel n is configured to operate in the nrz mode. 6be hdb3 enable: when set to 1 in the dual unipolar mode, the hdb3 codec is enabled. when set to 0, the interface codec is configured for ami. in the nrz mode, the state of this bit sets the tmoden output bit value (e.g., to enable an external hdb3 codec) when the fast sync feature is not selected. 5 reserved reserved: set to 0. 4 ensrai enable signaling highway remote alarm: enabled in the transmission mode. when set to 1, a remote alarm indication (bit 3 in time slot 0 of alter- nating frames) in the transmit signaling highway (tsigln) causes the remote alarm indication to be propagated to the line for channel n. 3 reserved reserved: set to 0. 2 ensais enable signaling highway ais: enabled in the transmission mode. when set to 1, an ais alarm detected in the transmit signaling highway (tsigln) causes the ais condition to be propagated to the line for channel n. 1lie general purpose interrupt input port (lint) enable: when set to 1, the active true state present on the general purpose interrupt input port (lintn pin) is logically or-gated with the internal los signal to form the los event and interrupt for channel n. control bit lpol (bit 0 in this register) deter- mines the active true sense. an active true signal also causes the clock refer- ence pins clkref1 (pin 46) and/or clkref2 (pin 2), when enabled, to be forced low. 0lpol general purpose interrupt input port (lint) polarity selection: when set to 1, a low present on the general purpose interrupt input port for channel n (lintn pin) is the active true state. when set to 0, a high present on the gen- eral purpose interrupt input port is the active true state. -139 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet 101 - ch 1 201 - ch 2 301 - ch 3 401 - ch 4 7txcp transmit clock polarity selection: when set to 1, data for channel n is clocked out to the line on the rising edges of the transmit clock (ltclkn). when set to 0, data is clocked out on the falling edges of the transmit clock (ltclkn). set to 0 for local loopback operation. 6rxcp receive clock polarity selection: when set to 1, data for channel n is clocked in from the line on the rising edges of the receive clock (lrclkn). when set to 0, data is clocked in on the falling edges of the receive clock (lrclkn). 5 txnrzp transmit nrz data polarity selection: when set to 1, the polarity of the transmit nrz data for channel n (tldatn) is inverted. 4pwrd power-down selection: when set to 0, the channel enters the inactivated low power state in both the transmit and receive directions. the transmit data value is determined by control bit fpol when forcing is enabled by control bit fdat. note: control bit fdat must be set to 1 in the power-down mode, otherwise the transmit data output state will be indeterminate. 3 fdat force transmit data: when set to 1, the transmit data state is forced to the state specified by control bit fpol. 2 fpol force transmit data polarity: this control bit is enabled when the fdat control bit is set to 1. when set to 1, transmit data output for channel n is set to 1 (ais). when set to 0, transmit data is set to 0. note: the forcing function occurs prior to the selected line encoding function. the following table is a summary of the actions taken by control bits fdat and fpol. f dat fpo l a ctio n 0 x normal operation. 1 0 transmit data set to 0. 1 1 transmit data set to 1. 1bnal bypass national bits: enabled in the transmission mode. when set to 1, the national bits from the signaling highway (tsigln) or microprocessor-writ- ten bits are used in place of the hdlc data link in the transmit direction. 0 rxnrzp receive nrz data polarity selection: when set to 1, the polarity of the received nrz data for channel n (rldatn) is inverted. address bit symbol description -140 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet 102 - ch 1 202 - ch 2 302 - ch 3 402 - ch 4 7-6 txc1-txc0 transmit clock selection: these two bits select the clock source for clock- ing out data from the transmit slip buffer to the line interface according to the following table: t xc1 txc0 tr a n s m i t clock s ource 0 0 local oscillator (lo). 0 1 system transmit clock (tclkn). only valid for 2 mbit/s mvip mode and transmission modes. 1 0 recovered receive line clock (lrclkn). 1 1 invalid combination (do not use). 5rxc receive clock select: this bit works in conjunction with control bit rse for selecting the clock (and sync) source for shifting data out of the receive slip buffer to the system. see bit 3 below. 4 tse transmit slip buffer enable: when set to 1, the transmit slip buffer is enabled. when set to 0, the transmit slip buffer is disabled, and data bypasses the slip buffer. this bit position must be written with a 1 in all oper- ating modes, except the 2 mbit/s transmission mode. 3 rse receive slip buffer enable: this bit works in conjunction with the rxc bit for enabling and disabling the receive slip buffer according to the following table. this bit position must be written with a 1 in all operating modes, except the 2 mbit/s transmission mode. r xc rse receive clock source/slip bu ffer 0 0 system receive clock (rclkn) and sync pulse (rsyncn); slip buffer disabled. use of this setting is not recommended. 0 1 system receive clock (rclkn) and sync pulse (rsyncn); slip buffer enabled. valid for all modes. 1 0 recovered receive clock (lrclkn) and internal sync pulse; slip buffer disabled. valid for 2 mbit/s transmis- sion mode only. 1 1 recovered receive clock (lrclkn) and internal sync pulse; slip buffer enabled. valid for 2 mbit/s transmis- sion mode only. note : rsyncn and rclkn pins are outputs when rxc is set to 1. 2 tsr transmit slip buffer recenter: when set to 1, this bit forces the transmit slip buffer to recenter. afterwards this bit should be written with a 0. while set to 0, the transmit slip buffer will recenter automatically to avoid the loss of data (programmed slip). 1rsr receive slip buffer recenter: when set to 1, this bit forces the receive slip buffer to recenter. afterwards this bit should be written with a 0. while set to 0, the receive slip buffer will recenter automatically to avoid the loss of data (programmed slip). 0fe1m fractional e1 mode: a 1 written to this bit position enables the transmit and receive fractional e1 feature for the channel. a gapped clock for the time slot(s) selected is provided on the rfe1gcn and tfe1gcn leads. receive time slots are selected by writing a 1 to or more control bits rfts0-rfts31 (x38h-x3bh). transmit time slots are selected by writing a 1 to one or more control bits tfts0-tfts31 (x3ch-x3fh). address bit symbol description -141 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet 103 - ch 1 203 - ch 2 303 - ch 3 403 - ch 4 7-6 typ1-typ0 signaling type selection: the following table lists the signaling selection formats in the transmit and receive directions that are controlled by bits typ1 and typ0. typ1 typ0 signaling type 0 0 time slot 16 assigned as a clear channel. 0 1 time slot 16 assigned for cas. abcd bits carried. abcd = 0000 from the transmit signaling highway (tsigln pins) or transmit signaling ram is transmitted as 1111. 1 0 time slot 16 assigned for cas. abcd bits carried. 1 1 time slot 16 cas invert mode. the abcd bits will be inverted from their present values. this option is effec- tive only for the transmit direction. the time slot 16 (ts16) multiframe alignment pattern is generated only when the cas or cas-inverted signaling types are selected. ts16 multi- frame alignment is meaningless in ts16 clear channel mode. ts16 multi- frame alignment is independent of device mode. 5rxf receive signaling freeze: when set to 1, the received line signaling bits are disabled from being written into the receive signaling registers. the con- tents present in the receive signaling registers before this bit was set will be used for the receive signaling highway. while frozen, the contents of the receive signaling registers (x80h through x8fh) may be altered by the microprocessor and these altered values will be repeated on the receive sig- naling highways. 4 txf transmit signaling freeze: when set to 1, the transmit signaling highway bits are disabled from being written into the transmit signaling registers. the contents present in the transmit signaling registers before this bit was set will be used for the transmit line. while frozen, the contents of the transmit sig- naling registers (xd0h through xdfh) may be altered by the microprocessor and these altered values will be repeated in time slot 16. this allows for trunk conditioning or signaling control to be accomplished. 3rx_sig_inv time slot 16 cas receive signaling invert: when set to 1, same as for typ1, typ0 = 11 above, except that it is effective for the receive direction only. 2enais enable ais: when set to 1, detection of a line ais causes the a-bits in the receive signaling highway rsigln to be set to 1 in the transmission modes. the a-bits are present in time slots 2 through 31 in the signaling highway format. when enais=1, ais will also be inserted on the receive data high- way when control bit stuais (bit 6) in register x07h is a 1 in any of the transmission, mvip, h-mvip/h.100 or 16 mbit/s pcm highway modes. 1enoof enable oof: when set to 1, detection of an out of frame alarm will cause the a-bits in the receive signal highway bit rsigln to be set to 1. the a-bits are present in time slots 2 through 31 in the signaling highway format. when enoof=1, ais will also be inserted on the receive data highway when control bit stuais (bit 6) in register x07h is a 1 in any system inter- face mode. address bit symbol description -142 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet 103 - ch 1 203 - ch 2 303 - ch 3 403 - ch 4 (cont.) 0 enlos enable los: when set to 1, detection of a loss of signal will cause the a- bits in the receive signal highway bit rsigln to be set to 1. the a-bits are present in time slots 2 through 31 in the signaling highway format. when enlos=1, ais will also be inserted on the receive data highway when con- trol bit stuais (bit 6) in register x07h is a 1 in any system interface mode. 104 - ch 1 204 - ch 2 304 - ch 3 404 - ch 4 7-6 oof1-oof0 out of frame detection criteria: the oof bits determine the out of frame detection criteria according to the following table: oof1 oo f0 o ut of fram e detection cr iteria 0 0 three consecutive fas patterns in error. 0 1 four consecutive fas patterns in error. 1 0 three consecutive fas patterns in error or three con- secutive nfas patterns in error. 1 1 four consecutive fas patterns in error or four consec- utive nfas patterns in error. the fas pattern is defined as x0011011, and the nfas pattern is defined as x1xxxxxx. these two patterns occur in alternating frames. 5bfaa basic frame alignment algorithm : when set to 0, the standard algorithm is selected. when set to 1, the frame hold-off algorithm is selected. note: when in a particular mode, a change in state of this bit will trigger a realign- ment procedure. the operations section describes the differences between the two modes (algorithms). 4 casa channel associated signaling alignment: when set to 0, the standard g.732 algorithm is selected. when set to 1, an enhanced algorithm is selected. note: when in a particular mode, a change in state of this bit will trigger a realignment procedure. the operations section describes the differences between the two modes (algorithms). 3 crca automatic crc-4/non-crc-4 mode selection: when set to 0, the non- crc-4 mode is selected. a search for the multiframe frame alignment is started in consecutive 8 ms periods. if alignment is not established in the 8 ms period, a new search is started. when set to 1 and control bit aags (bit 3 in register 0ffh) is set to 0, the automatic mode is selected for multiframe alignment. if alignment is not achieved in 400 ms, a non-crc-4 interworking (ncrc4) alarm indication (bit 7 in register x1bh) is set. the alarm inhibits further crc-4 processing and causes the e-bits in time slot 0 to be trans- mitted as zeros. note: when in a particular mode, a change in state of this bit will trigger a realignment procedure. see control bit aags description (bit 3 in register 0ffh) for operation when aags is set to 1. address bit symbol description -143 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet 104 - ch 1 204 - ch 2 304 - ch 3 404 - ch 4 (cont.) 2-1 crcmd1- crcmd0 crc framing mode: the crcmd1 and crcmd0 control bits determine the crc framing mode, according to the table given below: crcmd1 crcmd0 crc framing m ode 0 0 transparent (unframed) mode. 0 1 framed mode. crc-4 disabled. si bit used. 1 0 framed mode. crc-4 enabled. when in sync the e-bits carry the results to the distant end. when out of sync, the e-bits are 0. 1 1 framed mode. crc-4 enabled. the e-bits are always set to 1. 0rsyc resync enable: a 1 causes the framer to reset the frame alignment circuit, and start the search for a new frame alignment pattern. 11a - ch 1 21a - ch 2 31a - ch 3 41a - ch 4 7auty automatic y-bit response enable: the y-bit is defined as a remote multi- frame alarm indication in time slot 16. a 1 enables a loss of multiframe alignment, as selected by the eoo16m (bit 2) and eoocrc (bit 3) bits, on the receive side to cause the y-bit (bit 6) in time slot 16 in frame 0 of the multiframe to be transmitted as a 1. a 0 disables this automatic feature. note: the microprocessor can generate a remote multiframe alarm indica- tion independent of this feature by writing a 1 to control bit ts16ye (bit 5) in register x06h. 6 autrai automatic rai bit response enable: the rai bit is defined as a remote alarm indication, and it is carried in bit 3 in time slot 0 in the (nfas) frames which are not carrying the frame alignment pattern. a 1 enables a loss of basic frame alignment on the receive side to be transmitted as an rai on the transmit side. note: the microprocessor can generate a remote alarm indication indepen- dent of this feature by writing a 1 to control bit raie (bit 2) in register x07h. 5 enraia enable rai status from a-bit: a 1 enables the detection of the a-bit in the ts0 of odd-numbered frames to produce rai status (bit 4 in register x10h). 4 enraiy enable rai status from y-bit: a 1 enables the detection of the y-bit in ts16 to produce rai status (bit 4 in register x10h). address bit symbol description -144 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet 11a - ch 1 21a - ch 2 31a - ch 3 41a - ch 4 (cont.) 3 eoocrc enable out of multiframe alarm on loss of crc multiframe: a 1 enables a time slot 0 loss of crc multiframe to cause an out of multiframe alarm. when enabled, an out of multiframe alarm may also be caused by a time slot 0 loss of multiframe alignment. the following table summarizes the enable bits associated with the out of multiframe alarm. eoocrc eo o16m action 0 0 out of multiframe alarm disabled. 0 1 a time slot 16 loss of multiframe causes an out of multiframe alarm. 1 0 a time slot 0 loss of crc multiframe causes an out of multiframe alarm. 1 1 a time slot 16 loss of multiframe or a time slot 0 loss of crc multiframe causes an out of multiframe alarm. 2eoo16m enable out of multiframe alarm on time slot 16 loss of multiframe: a 1 enables a time slot 16 loss of multiframe to cause an out of multiframe alarm. when enabled, a out of multiframe alarm may also be caused by time slot 0 loss of crc multiframe alignment. the table given above sum- marizes the operation of this bit. 1e16ais enable ais indication on ais detected in time slot 16: a 1 enables an ais detected in time slot 16 to cause an ais alarm. when enabled, detec- tion of a line ais may be enabled to cause an ais alarm by setting bit enlais to 1. the following table summarizes the enable bits associated with the ais alarm. e16ais enlais action 0 0 ais alarm disabled. 0 1 line ais detected causes an ais alarm. 1 0 time slot 16 ais detected causes an ais alarm. 1 1 time slot 16 ais detected or line ais detected causes an ais alarm. 0enlais enable ais indication on line ais detected: a 1 enables detection of a line ais to cause an ais alarm, as shown in the above table. 138 - ch 1 238 - ch 2 338 - ch 3 438 - ch 4 7-0 rfts7- rfts0 receive enable fractional time slots 7-0: the receive fractional e1 mode is enabled when control bit fe1m is a 1, the config1 pin is low, and control bits hmvip and mtp16m are both set to 0 (2 mbit/s transmission mode). a 1 written to one or more bits enable a gapped clock (risgl/rfe1gc) to be generated for the corresponding time slots (7-0). 139 - ch 1 239 - ch 2 339 - ch 3 439 - ch 4 7-0 rfts15- rfts8 receive enable fractional time slots 15-8: the receive fractional e1 mode is enabled when control bit fe1m is a 1, the config1 pin is low, and control bits hmvip and mtp16m are both set to 0 (2 mbit/s transmission mode). a 1 written to one or more bits enable a gapped clock (risgl/ rfe1gc) to be generated for the corresponding time slots (15-8). address bit symbol description -145 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet 13a - ch 1 23a - ch 2 33a - ch 3 43a - ch 4 7-0 rfts23- rfts16 receive enable fractional time slots 23-16: the receive fractional e1 mode is enabled when control bit fe1m is a 1, the config1 pin is low/high, and control bits hmvip and mtp16m are both set to 0 (2 mbit/s transmis- sion mode or 2 mbit/s mvip mode). a 1 written to one or more bits enable a gapped clock (risgl/rfe1gc) to be generated for the corresponding time slots (23-16). 13b - ch 1 23b - ch 2 33b - ch 3 43b - ch 4 7-0 rfts31- rfts24 receive enable fractional time slots 31-24: the receive fractional e1 mode is enabled when control bit fe1m is a 1, the config1 pin is low/high, and control bits hmvip and mtp16m are both set to 0 (2 mbit/s transmis- sion mode or 2 mbit/s mvip mode). a 1 written to one or more bits enable a gapped clock (risgl/rfe1gc) to be generated for the corresponding time slots (31-24). 13c - ch 1 23c - ch 2 33c - ch 3 43c - ch 4 7-0 tfts7- tfts0 transmit enable fractional time slots 7-0: the transmit fractional e1 mode is enabled when control bit fe1m is a 1, the config1 pin is low/high, and control bits hmvip and mtp16m are both set to 0 (2 mbit/s transmis- sion mode or 2 mbit/s mvip mode). a 1 written to one or more bits enables a gapped clock (tisgl/tfe1gc) to be generated for the corresponding time slots (7-0). when control bit entslb is 1, these bits if set to 1 source time slots 7-1 from the receive data highway instead of tdatan pin. pins rclkn and rsyncn must be connected to pins tclkn and tsyncn respectively to prevent data errors in the looped back time slots. note: time slot 0 is generated by the framer and not taken from tdatan. 13d - ch 1 23d - ch 2 33d - ch 3 43d - ch 4 7-0 tfts15- tfts8 transmit enable fractional time slots 15-8: the transmit fractional e1 mode is enabled when control bit fe1m is a 1, the config1 pin is low/high, and control bits hmvip and mtp16m are both set to 0 (2 mbit/s transmis- sion mode or 2 mbit/s mvip mode). a 1 written to one or more bits enable a gapped clock (tisgl/tfe1gc) to be generated for the corresponding time slots (15-8). when control bit entslb is 1, these bits if set to 1 source time slots 15-8 from the receive data highway instead of tdatan pin. pins rclkn and rsyncn must be connected to pins tclkn and tsyncn respectively to prevent data errors in the looped back time slots. 13e - ch 1 23e - ch 2 33e - ch 3 43e - ch 4 7-0 tfts23- tfts16 transmit enable fractional time slots 23-16: the transmit fractional e1 mode is enabled when control bit fe1m is a 1, the config1 pin is low/high, and control bits hmvip and mtp16m are both set to 0 (2 mbit/s transmis- sion mode or 2 mbit/s mvip mode). a 1 written to one or more bits enable a gapped clock (tisgl/tfe1gc) to be generated for the corresponding time slots (23-16). when control bit entslb is 1, these bits if set to 1 source time slots 23-16 from the receive data highway instead of tdatan pin. pins rclkn and rsyncn must be connected to pins tclkn and tsyncn respectively to prevent data errors in the looped back time slots. address bit symbol description -146 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet software reset and loopback control register the control bits in the following read/write register are used to reset each of the channels, and to configure each of the channels within the qe1f- plus for the various loopback modes of operation. note that only one loopback is to be selected at any one time. 13f - ch 1 23f - ch 2 33f - ch 3 43f - ch 4 7-0 tfts31- tfts24 transmit enable fractional time slots 31-24: the transmit fractional e1 mode is enabled when control bit fe1m is a 1, the config1 pin is low/high, and control bits hmvip and mtp16m are both set to 0 (2 mbit/s transmis- sion mode or 2 mbit/s mvip mode). a 1 written to one or more bits enable a gapped clock (tisgl/tfe1gc) to be generated for the corresponding time slots (31-24). when control bit entslb is 1, these bits if set to 1 source time slots 31-24 from the receive data highway instead of tdatan pin. pins rclkn and rsyncn must be connected to pins tclkn and tsyncn respectively to prevent data errors in the looped back time slots. address bit symbol description 105 - ch 1 205 - ch 2 305 - ch 3 405 - ch 4 7srst software reset channel n: when set to 1, the channel is initialized and held in the reset state until a 0 is written into this bit position to per- mit commencement of channel operation. 6-4 reserved reserved: set to 0. 3payl payload remote loopback enable: when set to 1, the payload remote loopback feature is enabled until this bit position is written with a 0. the receive data is looped back as the transmit data for time slots 1 through 31 prior to the receive slip buffer input and in place of the trans- mit slip buffer output when this loopback feature is enabled. 2tx1s transmit ais (all ones): when set to 1 and control bit llp is set to 1, an ais (all ones) is transmitted instead of data. when set to 0, data is transmitted. 1rlp remote line loopback enable: when set to 1, the remote line loop- back feature is enabled until this bit position is written with a 0. receive line data (prior to the ami/hdb3 codec) is looped back as transmit line data when this loopback feature is enabled. 0llp local loopback enable: when set to 1, the local loopback feature is enabled until this bit position is written with a 0. transmit data (after the ami/hdb3 codec) is looped back as received data when this loop- back feature is enabled. when control bit tx1s (bit 2) is a 0 in x05h, data is transmitted. when tx1s is a 1, ais is transmitted. the ais sig- nal is defined as an all ones signal. address bit symbol description -147 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet system ais and test registers the control bits in the following read/write registers are used to generate test conditions and to configure the system interface for ais in channel (framer) n. address bit symbol description 106 - ch 1 206 - ch 2 306 - ch 3 406 - ch 4 7-6 reserved reserved: set to 0. 5 ts16ye generate time slot 16 remote alarm indication: when set to 1, the remote alarm indication, which is carried in bit 6 (y-bit) in time slot 16 in frame 0 of the multiframe, is transmitted as a 1 until the microproces- sor writes a 0 into this bit position. 4nfase generate bit 2 error in frames not carrying the frame alignment sequence: when set to 1, the transmit framer sends bit 2 in time slot 0 in alternating (nfas) frames as a 0, instead of the normal 1 value. to send a second nfas error, this bit has to be reset to 0 and then set to 1 again. 3insprbs insert pseudo-random bit sequence enable: when set to 1, prbs is inserted for the terminal data on the transmit data highway. this fea- ture is only available for 2 mbit/s transmission mode. to resume normal operation, this bit position must be written with a 0. 2sfz system freeze: when set to 1, the output clocks ltclkn and rclkn are forced to zero. the input clocks lrclkn and tclkn are gated off. to resume normal operation, this bit position must be written with a 0. 1rxfs receive fast sync enable: when set to 1, and the nrz mode is selected, a pulse received on the rnegn lead will force the synchroni- zation of this pulse to be interpreted as bit position 256 of the last frame (16) of a multiframe. when set to 0, coding violations indicated on the rnegn lead are counted. 0txfs transmit fast sync enable: when set to 1, and the nrz mode is selected, a synchronization pulse will be transmitted on the tnegn lead every two milliseconds in bit position 256 of frame 16. 107 - ch 1 207 - ch 2 307 - ch 3 407 - ch 4 7ais16 transmit time slot 16 ais enable: when set to 1, ais (all ones) is transmitted in time slot 16, including the multiframe alignment pattern in frame 0. ais is defined as all ones. ais is transmitted in time slot 16 until this bit is written with a 0. -148 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet 107 - ch 1 207 - ch 2 307 - ch 3 407 - ch 4 (cont.) 6stuais system tuais: when set to 1, the ais, oof and los alarms, if enabled by setting to 1 their respective enais (bit 2), enoof (bit 1), and enlos (bit 0) control bits in the signaling and time slot control register x03h, cause the generation of ais on the data highway for all six system interface modes of operation. the ais is sent until the alarm has recovered, or the enable bit (e.g., enais) is set to 0. the following table lists the operation of control bit enoof and this bit. control bits enais and enlos function in similar fashion. 2 mbit/s, 8 mbit/s and 16 mbit/s transmission modes enoof stuais action 0 0 no ais generated on signaling or data highway. 0 1 no ais generated on signaling or data highway. 1 0 ais generated only on signaling highway when oof alarm is detected. 1 1 ais generated on signaling and data highways when oof alarm is detected. 2 mbit/s mvip mode, 8 mbit/s h-mvip/h.100 mode and 16 pcm highway mode enoof stuais action 0 0 no ais generated on data highway. 0 1 no ais generated on data highway. 1 0 no ais generated on data highway even when oof alarm is detected. 1 1 ais generated on data highway when oof alarm is detected. note: the microprocessor can cause ais to be generated for the receive data highway independently of the two control bits by writing a 1 to control bit sysall1 (bit 5) in this register. 5 sysall1 send system ais: when set to 1, ais (all ones) is sent on the receive data highway. ais will be transmitted on the receive data highway until this bit is written with a 0. 4crc generate a crc-4 error: this feature is enabled when control bits crcmd1 and crcmd0 (bits 2 and 1) in register x04h are equal to 10, or 11 (i.e., this enables the crc-4 feature). when crc is set to 1, the crc-4 bits in time slot 0 are transmitted in the inverted state once. to send another crc-4 error, this bit must be first written with a 0, and then a 1. 3fase generate a frame alignment sequence error: when set to 1, the transmitter will send the 7-bit frame alignment pattern in time slot 0 in alternating (fas) frames in error once. all the bits in the frame align- ment sequence are inverted once (x0011011 becomes x1100100). to send another frame alignment sequence error, this bit must be first writ- ten with a 0, and then a 1. address bit symbol description -149 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet e1 status and mask registers these registers are read/write, except for registers x10h, which are read-only unlatched. the status bits in the x11h register represent the latched status indications generated by the channel alarms. the bits latch on either the rising edge, the falling edge, or both edges of the current status or interrupt request event bits as defined by the rise/fall control bits (bits 6 and 5) in the global configuration register 006h. a latched bit will cause a hardware interrupt indication when the global interrupt mask bit gim (bit 7) in register 006h and the corresponding masks bit in the mask registers x09h and 00b are both written with a 0. the bits in register x10h represent the current (unlatched) alarm status. a latched status bit is reset by writing a 0 into the latched bit position, or by the rising edge of the t1si pulse when the performance monitoring/fault monitoring feature is enabled. this feature activates the shadow registers x12h and x13h, and it is enabled by writing a 1 to control bit enpmfm (bit 3) in the global configuration register 006h. 107 - ch 1 207 - ch 2 307 - ch 3 407 - ch 4 (cont.) 2raie generate remote alarm indication: when set to 1, the remote alarm indication, which is carried in bit 3 in time slot 0 of those (nfas) frames not carrying the frame alignment sequence, is transmitted as a 1 until the microprocessor writes a 0 into this bit position. 1aise transmit line ais enable: when set to 1, a line ais is transmitted. a line ais is defined as all ones transmitted in the frame. line ais is trans- mitted until this bit is written with a 0. 0bpv generate bipolar violation (bpv) error: when the dual unipolar mode is selected by bit 7 in register x00h, a 1 in this bit position causes a single bpv error to be sent. the microprocessor must write a 0 to this bit before another bpv error can be transmitted by setting it to 1. in ran- dom data the bpv may mimic a valid zero substitution code in hdb3 mode and may not be detected as an error. address bit symbol description 109 - ch 1 209 - ch 2 309 - ch 3 409 - ch 4 7mlos loss of signal (los) mask bit: when set to 1, detection of a loss of signal alarm is masked from providing a hardware interrupt. 6mais ais mask bit: when set to 1, detection of an ais condition is masked from providing a hardware interrupt. 5moof out of frame (oof) mask bit: when set to 1, detection of an out of frame alarm is masked from providing a hardware interrupt. 4mrai remote alarm indication (rai) mask bit: when set to 1, detection of a remote alarm indication is masked from providing a hardware interrupt. 3mcfa change in frame alignment (cfa) mask bit: when set to 1, detection of a change in frame alignment indication is masked from providing a hardware interrupt. 2moomf out of multiframe alignment (oomf) mask bit: when set to 1, detection of an out of multiframe alarm is masked from providing a hardware interrupt. 1mtxslip transmit slip indication mask bit: when set to 1, detection of a transmit slip is masked from providing a hardware interrupt. 0 mrxslip receive slip indication mask bit: when set to 1, detection of a receive slip is masked from providing a hardware interrupt. address bit symbol description -150 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet 110 - ch 1 210 - ch 2 310 - ch 3 410 - ch 4 7los loss of signal (los) alarm (unlatched): a 1 indicates a loss of signal has been detected. a loss of signal alarm is detected when the incoming signal for the rail interface only has no transitions for n consecutive pulse positions, where the value of n is programmable between 10 and 255. the binary value written to losi7-losi0 (bits 7-0) in register 01ah selects the value of n. the los alarm is cleared when at least m ones are detected in an interval of n pulse positions, where m is the value written to ond5-ond0 in bits 5-0 of reg- ister 01bh. in addition, an external los indication from the external line trans- ceiver (using the lintn pin) can be or-gated with this alarm by setting control bit lie (bit 1) in register x00h to 1. 6ais ais indication (unlatched): a 1 indicates that a line alarm indication signal (ais) and/or an ais in time slot 16 has been detected. control bit enlais (bit 0) in register x1ah enables a line ais alarm. control bit e16ais (bit 1) in register x1ah enables a receive time slot 16 ais alarm. a line ais is detected when the received line signal has two or less zeros in each of two consecutive double-frame periods (512 bits). recovery occurs when each of two consecutive double-frame periods contain three or more zeros after frame alignment has been detected. an ais in time slot 16 is detected when the received time slot has detected three or less zeros in each of two consecutive multiframe periods. recovery occurs when each of two consecutive multi- frame periods contains four or more zeros or when the multiframe alignment signal has been detected. 5oof out of frame (oof) alarm (unlatched): a 1 indicates that an out of frame alarm has been detected. the alarm is programmed using the oof1 and oof0 control bits (bits 7 and 6) in register x04h. the qe1f- plus supports two recovery schemes, with or without the crc-4 check. this is controlled by control bit bfaa (bit 5) in the register x04h. 4rai remote alarm indication (rai) (unlatched): a 1 indicates that the received rai bit is a 1 for four or more consecutive frames in which it is carried. the rai bit is bit 3 in time slot 0, in those alternate (nfas) frames that are not carrying the frame alignment pattern, or the y-bit of ts16. recovery occurs when the rai bit is 0 for four (nfas) or three (y-bit) or more consecutive frames in which it is carried. control bit enraiy (bit 4 of register x1ah) enables this alarm if the y-bit in time slot 16 is set. control bit enraia (bit 5 of register x1ah) enables this alarm if the a-bit in time slot 0 is set. 3cfa change in frame alignment (cfa) indication (unlatched): a 1 indicates that the frame alignment circuit has detected a change in the frame alignment pattern only after frame alignment has been detected. 2oomf out of multiframe alignment (oomf) alarm (unlatched): a 1 indicates that time slot 16 multiframe alignment has been lost and/or a crc-4 multi- frame alignment has been also lost. control bit eoocrc (bit 3) in register x1ah enables a loss of crc-4 multiframe alignment alarm. control bit eoo16m (bit 2) in x1ah enables a ts16 multiframe alarm. 1txslip transmit slip indication (unlatched): this bit reflects the current status of the transmit slip buffer with respect to a slip being executed in the previous 125 microseconds. address bit symbol description -151 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet 110 - ch 1 210 - ch 2 310 - ch 3 410 - ch 4 (cont.) 0rxslip receive slip indication (unlatched): this bit reflects the current status of the receive slip buffer with respect to a slip being executed in the previous 125 microseconds. 111 - ch 1 211 - ch 2 311 - ch 3 411 - ch 4 7llos latched loss of signal (los): this bit is set to 1 on an active edge of los which is selected by the rise (bit 6) and fall (bit 5) bits in the global config- uration register 006h. if not masked by the corresponding mask bit in register x09h or the gim bit in register 006h, an interrupt is generated. this bit is cleared by writing a 0 into this bit position. 6lais latched ais: this bit is set to 1 on an active edge of ais which is selected by the rise (bit 6) and fall (bit 5) bits in the global configuration register 006h. if not masked by the corresponding mask bit in register x09h or the gim bit in register 006h, an interrupt is generated. this bit is cleared by writ- ing a 0 into this bit position. 5loof latched out of frame (oof): this bit is set to 1 on an active edge of oof which is selected by the rise (bit 6) and fall (bit 5) bits in the global config- uration register 006h. if not masked by the corresponding mask bit in register x09h or the gim bit in register 006h, an interrupt is generated. this bit is cleared by writing a 0 into this bit position. 4lrai latched remote alarm indication (rai): this bit is set to 1 on an active edge of rai which is selected by the rise (bit 6) and fall (bit 5) bits in the global configuration register 006h. if not masked by the corresponding mask bit in register x09h or the gim bit in register 006h, an interrupt is generated. this bit is cleared by writing a 0 into this bit position. 3lcfa latched change in frame alignment (cfa) mask bit: this bit is set to 1 on an active edge of cfa which is selected by the rise (bit 6) and fall (bit 5) bits in the global configuration register 006h. if not masked by the corre- sponding mask bit in register x09h or the gim bit in register 006h, an inter- rupt is generated. this bit is cleared by writing a 0 into this bit position. 2 loomf latched out of multiframe alignment (oomf): this bit is set to 1 on an active edge of oomf which is selected by the rise (bit 6) and fall (bit 5) bits in the global configuration register 006h. if not masked by the corre- sponding mask bit in register x09h or the gim bit in register 006h, an inter- rupt is generated. this bit is cleared by writing a 0 into this bit position. 1ltxslip latched transmit slip indication: this bit is set to 1 on an active edge of txslip which is selected by the rise (bit 6) and fall (bit 5) bits in the glo- bal configuration register, location 006h. if not masked by the corresponding mask bit in register x09h or the gim bit in register 006h, an interrupt is gener- ated. this bit is cleared by writing a 0 into this bit position. 0lrxslip latched receive slip indication: this bit is set to 1 on an active edge of rxslip which is selected by the rise (bit 6) and fall (bit 5) bits in the glo- bal configuration register 006h. if not masked by the corresponding mask bit in register x09h or the gim bit in register 006h, an interrupt is generated. this bit is cleared by writing a 0 into this bit position. address bit symbol description -152 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet 112 - ch 1 212 - ch 2 312 - ch 3 412 - ch 4 7plos loss of signal (los) one second error: this bit is set to 1 if the los alarm occurred at any time in the last one second interval. the t1si signal must be present and control bit enpmfm (bit 3) in the global configuration register x006h must be set to 1. 6pais ais one second error: this bit is set to 1 if the ais indication occurred at any time in the last one second interval. the t1si signal must be present and control bit enpmfm (bit 3) in the global configuration register 006h must be set to 1. 5poof out of frame (oof) one second error: this bit is set to 1 if the oof alarm occurred at any time in the last one second interval. the t1si signal must be present and control bit enpmfm (bit 3) in the global configuration register 006h must be set to 1. 4prai remote alarm indication (rai) one second error: this bit is set to 1 if the rai indication occurred at any time in the last one second interval. the t1si signal must be present and control bit enpmfm (bit 3) in the global configu- ration register 006h must be set to 1. 3pcfa change in frame alignment (cfa) one second error: this bit is set to 1 if the cfa indication occurred at any time in the last one second interval. the t1si signal must be present and control bit enpmfm (bit 3) in the global configuration register 006h must be set to 1. 2poomf out of multiframe alignment (oomf) one second error: this bit is set to 1 if the oomf alarm occurred at any time in the last one second interval. the t1si signal must be present and control bit enpmfm (bit 3) in the global configuration register 006h must be set to 1. 1ptxslip transmit slip indication one second error: this bit is set to 1 if the txslip indication occurred at any time in the last one second interval. the t1si signal must be present and control bit enpmfm (bit 3) in the global configuration register x006h must be set to 1. 0prxslip receive slip indication one second error: this bit is set to 1 if the rxslip indication occurred at any time in the last one second interval. the t1si signal must be present and control bit enpmfm (bit 3) in the global configuration register 006h must be set to 1. address bit symbol description -153 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet 113 - ch 1 213 - ch 2 313 - ch 3 413 - ch 4 7flos loss of signal (los) persistent error: this bit is set to 1 if the los alarm is active but did not become active in the last one second interval. the t1si signal must be present and control bit enpmfm (bit 3) in the global configuration register 006h must be set to 1. 6fais ais persistent error: this bit is set to 1 if the ais indication is active but did not become active in the last one second interval. the t1si signal must be present and control bit enpmfm (bit 3) in the global configuration register 006h must be set to 1. 5foof out of frame (oof) persistent error: this bit is set to 1 if the oof alarm is active but did not become active in the last one second interval. the t1si signal must be present and control bit enpmfm (bit 3) in the global configuration register x006h must be set to 1. 4frai remote alarm indication (rai) persistent error: this bit is set to 1 if the rai indication is active but did not become active in the last one second inter- val. the t1si signal must be present and control bit enpmfm (bit 3) in the global configuration register 006h must be set to 1. 3fcfa change in frame alignment (cfa) persistent error: this bit is set to 1 if the cfa indication is active but did not become active in the last one second interval. the t1si signal must be present and control bit enpmfm (bit 3) in the global configuration register x006h must be set to 1. 2 foomf out of multiframe alignment (oomf) persistent error: this bit is set to 1 if the oomf alarm is active but did not become active in the last one second interval. the t1si signal must be present and control bit enpmfm (bit 3) in the global configuration register 006h must be set to 1. 1 ftxslip transmit slip indication persistent error: this bit is set to 1 if the txslip indication is active but did not become active in the last one second interval. the t1si signal must be present and control bit enpmfm (bit 3) in the global configuration register 006h must be set to 1. 0frxslip receive slip indication persistent error: this bit is set to 1 if the rxslip indication is active but did not become active in the last one second interval. the t1si signal must be present and control bit enpmfm (bit 3) in the global configuration register 006h must be set to 1. address bit symbol description -154 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet counters and counter shadow registers the qe1f- plus provides counter and counter shadow read/write registers for e-bit errors, crc-4 bit errors, coding violations, and framing bit errors. the counter shadow registers provide the microprocessor with an error count for the previous one second interval. a counter and the corresponding counter shadow register (and their overflow bits) are cleared when the microprocessor writes 0 to their bits. the rising edges of a one second interval pulse clear the counters (and the overflow bits, if set). the shadow registers for the various counters are also updated at one second intervals by the rising edge of the pulse applied to the t1si pin (pin 40). address bit symbol description 1ec - ch 1 2ec - ch 2 3ec - ch 3 4ec - ch 4 7-0 lebe7-lebe0 latched e-bit error counter shadow register: this register contains the lower 8 bits of the 10-bit shadow register assigned for holding the e- bit error count that occurred in the previous one second interval. this location is updated from ebe7-ebe0 with a new count at one second intervals on the rising edges of the t1si signal if control bit enpmfm is set to a 1. bit 0 is the lsb of the 10-bit count. 1ed - ch 1 2ed - ch 2 3ed - ch 3 4ed - ch 4 7 lebeo latched e-bit error counter overflow bit: this bit contains the overflow indication associated with the 10-bit shadow register lebe9- lebe0 assigned for holding the e-bit error count that occurred in the previous one second interval. this location is updated from ebeo at one second intervals on the rising edges of the t1si signal if control bit enpmfm is set to a 1. 6-2 reserved reserved : set to 0. 1-0 lebe9-lebe8 latched e-bit error counter shadow register: this register contains the upper two bits of the 10-bit shadow register assigned for holding the e-bit error count that occurred in the previous one second interval. this location is updated from ebe9-ebe8 with a new count at one second intervals on the rising edges of the t1si signal if control bit enpmfm is set to a 1. bit 1 is the msb of the 10-bit count. 1ee - ch 1 2ee - ch 2 3ee - ch 3 4ee - ch 4 7-0 ebe7-ebe0 e-bit error counter: this register contains the lower 8 bits of the 10-bit e-bit error counter. when enabled (control bits crcmd1,0 bits 2 and 1 in register x04h = 10), this counter increments for every received e-bit which is 0, after crc-4 multiframe alignment is achieved and oof or ais is not detected. this location is cleared at one second intervals between the rising and falling edges of the t1si signal if control bit enpmfm is set to a 1. bit 0 is the lsb of the 10-bit count. 1ef - ch 1 2ef - ch 2 3ef - ch 3 4ef - ch 4 7ebeo e-bit error counter overflow bit: this bit contains the overflow indica- tion associated with the 10-bit e-bit counter ebe9-ebe0. this bit sets when the 10-bit counter overflows. it will remain set until the microproces- sor writes a 0 into this location. this location is also cleared at one sec- ond intervals on the rising edges of the t1si signal if control bit enpmfm is set to a 1. 6-2 reserved reserved : set to 0. -155 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet 1ef - ch 1 2ef - ch 2 3ef - ch 3 4ef - ch 4 (cont.) 1-0 ebe9-ebe8 e-bit error counter: this register contains the upper 2 bits of the 10-bit e-bit error counter. when enabled (control bits crcmd1,0 bits 2 and 1 in register x04h = 10), this counter increments for every received e-bit which is 0, after crc-4 multiframe alignment is achieved and oof or ais is not detected. this location is cleared at one second intervals on the ris- ing edges of the t1si signal if control bit enpmfm is set to a 1. bit 1 is the msb of the 10-bit count. 1f0 - ch 1 2f0 - ch 2 3f0 - ch 3 4f0 - ch 4 7-0 lcrc7- lcrc0 latched crc-4 error counter shadow register: this register con- tains the lower 8 bits of the 10-bit shadow register assigned for holding the crc-4 error count that occurred in the previous one second interval. this location is updated from crc7-crc0 with a new count at one sec- ond intervals on the rising edges of the t1si signal if control bit enpmfm is set to a 1. bit 0 is the lsb of the 10-bit count. 1f1 - ch 1 2f1 - ch 2 3f1 - ch 3 4f1 - ch 4 7 lcrco latched crc-4 error counter overflow bit: this bit contains the over- flow indication associated with the 10-bit shadow register lcrc9-lcrc0 assigned for holding the crc-4 error count that occurred in the previous one second interval. this location is updated from crco at one second intervals on the rising edges of the t1si signal if control bit enpmfm is set to a 1. 6-2 reserved reserved : set to 0. 1-0 lcrc9- lcrc8 latched crc-4 error counter shadow register: this register con- tains the upper two bits of the 10-bit shadow register assigned for holding the crc-4 error count that occurred in the previous one second interval. this location is updated from crc9-crc8 with a new count at one sec- ond intervals on the rising edges of the t1si signal if control bit enpmfm is set to a 1. bit 1 is the msb of the 10-bit count. 1f2 - ch 1 2f2 - ch 2 3f2 - ch 3 4f2 - ch 4 7-0 crc7-crc0 crc-4 error counter: this register contains the lower 8 bits of the 10-bit crc-4 error counter. this location is cleared at one second intervals on the rising edges of the t1si signal if control bit enpmfm is set to a 1. bit 0 is the lsb of the 10-bit count. 1f3 - ch 1 2f3 - ch 2 3f3 - ch 3 4f3 - ch 4 7crco crc-4 error counter overflow bit: this bit contains the overflow indi- cation associated with the 10-bit crc-4 counter crc9-crc0. this bit sets when the 10-bit counter overflows. it will remain set until the micro- processor writes a 0 into this location. this location is also cleared at one second intervals on the rising edges of the t1si signal if control bit enp- mfm is set to a 1. 6-2 reserved reserved : set to 0. 1-0 crc9-crc8 crc-4 error counter: this register contains the upper 2 bits of the 10-bit crc-4 error counter. this location is cleared at one second inter- vals on the rising edges of the t1si signal if control bit enpmfm is set to a 1. bit 1 is the msb of the 10-bit count. address bit symbol description -156 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet 1f4 - ch 1 2f4 - ch 2 3f4 - ch 3 4f4 - ch 4 7-0 lcv7-lcv0 latched coding violation counter shadow register: this register contains the lower 8 bits of the 16-bit shadow register assigned for hold- ing the hdb3 coding violation count that occurred in the previous one second interval. this location is updated from cv7-cv0 with a new count at one second intervals on the rising edges of the t1si signal if control bit enpmfm is set to a 1. bit 0 is the lsb of the 16-bit count. 1f5 - ch 1 2f5 - ch 2 3f5 - ch 3 4f5 - ch 4 7-0 lcv15-lcv8 latched coding violation counter shadow register: this register contains the upper 8 bits of the 16-bit shadow register assigned for hold- ing the hdb3 coding violation count that occurred in the previous one second interval. this location is updated from cv15-cv8 with a new count at one second intervals on the rising edges of the t1si signal if control bit enpmfm is set to a 1. bit 7 is the msb of the 16-bit count. 1f6 - ch 1 2f6 - ch 2 3f6 - ch 3 4f6 - ch 4 7lcvo latched coding violation counter overflow bit: this bit contains the overflow indication associated with the 16-bit shadow register lcv15- lcv0 assigned for holding the coding violation count that occurred in the previous one second interval. this location is updated from cvo at one second intervals on the rising edges of the t1si signal if control bit enp- mfm is set to a 1. 6-0 reserved reserved : set to 0. 1f7 - ch 1 2f7 - ch 2 3f7 - ch 3 4f7 - ch 4 7-0 cv7-cv0 coding violation counter: this register contains the lower 8 bits of the 16-bit hdb3 coding violation counter. this location is cleared at one sec- ond intervals on the rising edges of the t1si signal if control bit enpmfm is set to a 1. bit 0 is the lsb of the 16-bit count. 1f8 - ch 1 2f8 - ch 2 3f8 - ch 3 4f8 - ch 4 7-0 cv15-cv8 coding violation counter: this register contains the upper 8 bits of the 16-bit hdb3 coding violation counter. this location is cleared at one second intervals on the rising edges of the t1si signal if control bit enpmfm is set to a 1. bit 7 is the msb of the 16-bit count. 1f9 - ch 1 2f9 - ch 2 3f9 - ch 3 4f9 - ch 4 7cvo coding violation counter overflow bit: this bit contains the overflow indication associated with the 16-bit coding violation counter cv15-cv0. this bit sets when the 16-bit counter overflows. it will remain set until the microprocessor writes a 0 into this location. this location is also cleared at one second intervals on the rising edges of the t1si signal if control bit enpmfm is set to a 1. 6-0 reserved reserved : set to 0. 1fa - ch 1 2fa - ch 2 3fa - ch 3 4fa - ch 4 7-0 lfbe7-lfbe0 latched framing error counter shadow register: this register con- tains the lower 8 bits of the 13-bit shadow register assigned for holding the framing word errors that occurred in the previous one second interval. this location is updated from fbe7-fbe0 with a new count at one sec- ond intervals on the rising edges of the t1si signal if control bit enpmfm is set to a 1. address bit symbol description -157 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet 1fb - ch 1 2fb - ch 2 3fb - ch 3 4fb - ch 4 7lfbeo latched framing error counter overflow bit: this bit contains the overflow indication associated with the 13-bit shadow register lfbe12- lfbe0 assigned for holding the framing word error count that occurred in the previous one second interval. this location is updated from fbeo at one second intervals on the rising edges of the t1si signal if control bit enpmfm is set to a 1. 6-5 reserved reserved : set to 0. 4-0 lfbe12- lfbe8 latched framing error counter shadow register: this register con- tains the upper 5 bits of the shadow register assigned for holding the framing word errors that occurred in the previous one second interval. this location is updated from fbe12-fbe8 with a new count at one sec- ond intervals on the rising edges of the t1si signal if control bit enpmfm is set to a 1. bit 4 is the msb of the 13-bit count. 1fc - ch 1 2fc - ch 2 3fc - ch 3 4fc - ch 4 7-0 fbe7-fbe0 framing error counter: this register contains the lower 8 bits of the 13- bit framing word error counter. an incorrectly received fas word in time slot 0 is counted as one frame word error. a frame word error is also counted if bit 2 of the nfas pattern in time slot 0 is not a 1. this location is cleared at one second intervals on the rising edges of the t1si signal if control bit enpmfm is set to a 1. 1fd - ch 1 2fd - ch 2 3fd - ch 3 4fd - ch 4 7fbeo framing error counter overflow bit: this bit contains the overflow indication associated with the 13-bit framing word error counter fbe12- fbe0. this bit sets when the 13-bit counter overflows. it will remain set until the microprocessor writes a 0 into this location. this location is also cleared at one second intervals on the rising edges of the t1si signal if control bit enpmfm is set to a 1. 6-5 reserved reserved : set to 0. 4-0 fbe12-fbe8 framing error counter: this register contains the upper 5 bits of the 13- bit framing word error counter. an incorrectly received fas word in time slot 0 is counted as one frame word error. a frame word error is also counted if bit 2 of the nfas pattern in time slot 0 is not a 1. this location is cleared at one second intervals on the rising edges of the t1si signal if control bit enpmfm is set to a 1. bit 4 is the msb of the 13-bit count. address bit symbol description -158 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet operational status registers the status bits in the following read-only unlatched registers indicate various status information associated with the transmit and receive two-frame slip buffers. the slip buffers are always enabled in the mvip, h-mvip/ h.100 and 16 mbit/s pcm highway modes (config1 pin is high - pin 43). the slip buffers are optional in the transmission modes (config1 pin is low - pin 43). the transmit slip buffer is enabled when a 1 is written into control bit tse (bit 4) in register x02h. the receive slip buffer is enabled when a 1 is written into control bit rse (bit 3) in register x02h. address bit symbol description 114 - ch 1 214 - ch 2 314 - ch 3 414 - ch 4 7-6 txs1-tsx0 transmit slip buffer status: the following table indicates the direction of a transmit slip. a transmit slip indication (unlatched) is provided by status bit txslip (bit 1) set to 1 in register x10h. a latched indication is given by ltxslip (bit 1) set to 1 in register x11h. txs1 txso buffer status 0 0 no slips have occurred. 0 1 slip overflow. one frame dropped. 1 0 slip underflow. one frame repeated. 1 1 slip buffer error. two slips in a row. 5-4 rxs1-rxs0 receive slip buffer status: the following table indicates the direction of a receive slip. a receive slip indication (unlatched) is provided by status bit rxslip (bit 0) set to 1 in register x10h. a latched indication is given by lrxslip (bit 0) set to 1 in register x11h. rxs1 rxso buffer status 0 0 no slips have occurred. 0 1 slip overflow. one frame dropped. 1 0 slip underflow. one frame repeated. 1 1 slip buffer error. two slips in a row. 3 tuais tu ais received: this status bit is enabled in the transmission modes only. a 1 indicates that the (ais) a-bits on the transmit signaling highway (tsigln) are set to 1. the response time and recovery times are immedi- ate. 2 turai tu rai received: this status bit is enabled in the transmission modes only. a 1 indicates that the remote alarm indication (rai) bit (bit 3 in time slot 0 in alternating nfas frames) on the transmit signaling highway (tsigln) is set to 1. the response time and recovery times are immediate. 1-0 reserved reserved : disregard these bits. -159 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet 115 - ch 1 215 - ch 2 315 - ch 3 415 - ch 4 7rxsf receive signaling freeze indication: when set to 1, this status bit indi- cates that the receive signaling bits in the signaling buffer are frozen as a result of a loss of signal, an out of frame alarm, or control bit rxf (bit 5) in register x03h being set to a 1. 6txsf transmit signaling freeze indication: when set to 1, this status bit indi- cates that the transmit signaling bits in the signaling buffer are frozen as a result of receiving an ais indication on the signaling highway in the trans- mission mode, or control bit txf (bit 4) in register x03h is a 1. 5-1 reserved reserved : disregard these bits. 0lint general purpose input status indication: the status of this bit reflects the state of the external input pin lintn. the input polarity (i.e., active true state) of this pin is determined by control bit lpol (bit 0) in register x00h. 11b - ch 1 21b - ch 2 31b - ch 3 41b - ch 4 7 ncrc4 non-crc4 interworking: a 1 indicates that a crc-4 to non-crc-4 inter- working has been established. when 0, this bit indicates that a crc-4 interworking has been established. the status becomes valid after a one second interval when control bit crca (bit 3) in register x04h is 1. the status of this bit should be disregarded when control bit crca is 0. 6ecrce receive excessive crc-4 errors: a 1 indicates that 915 or more of the last 1000 crc-4 received were in error. a 0 indicates that the number of crc-4 errors was below this level. if set to a 1, this bit will clear several frames after basic frame alignment is regained. 5raia remote alarm indication (rai) from a-bit: this bit is set to 1 when rai status occurs due to detection of the a-bit in the ts0 of even-numbered frames. 4 ts16me time slot 16 multiframe error: this bit is set to 1 when a multiframe error is detected in the time slot 16 multiframe. 3 oocrcm crc-4 multiframe out of frame: this bit reflects the status of the crc-4 multiframe out of frame detector. a 1 indicates out of crc-4 multiframe detection. 2oots16m time slot 16 multiframe out of frame: this bit reflects the status of the channel associated signaling multiframe detector. a 1 indicates out of time slot 16 multiframe detection. 1ts16ais time slot 16 ais detection: this bit reflects the status of the ais detector for time slot 16. a 1 indicates time slot 16 ais detection. 0lineais line ais detection: this bit reflects the status of the line ais detector for the e1 frame format. a 1 indicates line ais detection. address bit symbol description -160 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet slip buffer pointer status registers the following unlatched register locations provide receive read and write pointer information, and transmit read and write pointer information, from the receive and transmit slip buffers respectively. although these registers are writable, writing to these registers will cause a slip to occur. address bit symbol description 120 - ch 1 220 - ch 2 320 - ch 3 420 - ch 4 7-0 twp7-twp0 transmit slip buffer write pointer: bit 0 is the lsb. the value (between 0 and 255) is the current value of the transmit slip buffer write pointer. 121 - ch 1 221 - ch 2 321 - ch 3 421 - ch 4 7-0 trp7-trp0 transmit slip buffer read pointer: bit 0 is the lsb. the value (between 0 and 255) is the current value of the transmit slip buffer read pointer. 122 - ch 1 222 - ch 2 322 - ch 3 422 - ch 4 7twsbs transmit slip buffer write side: a 1 indicates that the upper side of the transmit buffer is currently being written, a 0 indicates that the lower side of the transmit buffer is being written. 6-4 reserved reserved : disregard these bits. 3-0 twpf3-twpf0 transmit slip buffer write pointer frame: the bits in these locations indicate for which frame the transmit slip buffer write pointer is being written. for the basic frame format, there are two values (0000 = frame 0 and 0001 = frame 1). for the crc-4 multiframe format the value will range between 0 and 15. bit 0 is the lsb. 123 - ch 1 223 - ch 2 323 - ch 3 423 - ch 4 7trsbs transmit slip buffer read side: a 1 indicates that the upper side of the transmit buffer is currently being read, a 0 indicates that the lower side of the transmit buffer is being read. 6-4 reserved reserved : disregard these bits. 3-0 trpf3-trpf0 transmit slip buffer read pointer frame: the bits in these locations indicate for which frame the transmit slip buffer read pointer is being read. for the basic frame format, there are two values (0000 = frame 0 and 0001 = frame 1). for the crc-4 multiframe format the value will range between 0 and 15. bit 0 is the lsb. 124 - ch 1 224 - ch 2 324 - ch 3 424 - ch 4 7-0 rwp7-rwp0 receive slip buffer write pointer: bit 0 is the lsb. the value (between 0 and 255) is the current value of the receive slip buffer write pointer. 125 - ch 1 225 - ch 2 325 - ch 3 425 - ch 4 7-0 rrp7-rrp0 receive slip buffer read pointer: bit 0 is the lsb. the value (between 0 and 255) is the current value of the receive slip buffer read pointer. -161 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet receive time slot control registers the control bits in the following read/write registers are used to enable or disable (freeze) the receive buffer locations for the system highway, and to allow the microprocessor to write in service codes and idle codes. 126 - ch 1 226 - ch 2 326 - ch 3 426 - ch 4 7rwsbs receive slip buffer write side: a 1 indicates that the upper side of the receive buffer is currently being written. a 0 indicates that the lower side of the receive buffer is being written. 6-4 reserved reserved : disregard these bits. 3-0 rwpf3- rwpf0 receive slip buffer write pointer frame: the bits in these locations indicate for which frame the receive slip buffer write pointer is being writ- ten. for the basic frame format, there are two values (0000 = frame 0 and 0001 = frame 1). for the crc-4 multiframe format the value will range between 0 and 15. bit 0 is the lsb. 127 - ch 1 227 - ch 2 327 - ch 3 427 - ch 4 7 rrsbs receive slip buffer read side: a 1 indicates that the upper side of the receive buffer is currently being read, a 0 indicates that the lower side of the receive buffer is being read. 6-4 reserved reserved : disregard these bits. 3-0 rrpf3-rrpf0 receive slip buffer read pointer frame: the bits in these locations indicate for which frame the receive slip buffer read pointer is being read. for the basic frame format, there are two values (0000 = frame 0 and 0001 = frame 1). for the crc-4 multiframe format the value will range between 0 and 15. bit 0 is the lsb. address bit symbol description 12a - ch 1 22a - ch 2 32a - ch 3 42a - ch 4 7rsis receive international bits (si) select: when set to 1, the two interna- tional bits received from the line (in bit 1 of time slot 0 in alternating fas and nfas frames) are sent to the receive signaling highway and to the data highway, via a buffer. when set to 0, the received international bits are disabled from being written into the buffer, and the value sitting in the buffer is frozen. the value of these bits in the buffer may now be rewritten by the microprocessor. the buffer location of time slot 0 is register x40h for (fas) frames carrying the frame alignment pattern, and x60h for (nfas) frames not carrying the frame alignment pattern. 6-5 reserved reserved: set to 0. 4-0 rsa4s-rsa8s receive national bits (sa4-sa8) select: bit 4 corresponds to the received sa4 bit in time slot 0 of nfas frames. when a bit is set to 1, the corresponding national bit received in time slot 0 is sent to the receive signaling highway and to the data highway, via a buffer. when set to 0, the received national bit is disabled from being written into the buffer, and the value sitting in the buffer is frozen. the value of the bit in the buffer may be rewritten by the microprocessor. the buffer location is register x60h. address bit symbol description -162 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet 12b - ch 1 22b - ch 2 32b - ch 3 42b - ch 4 7-3 reserved reserved: set to 0. 2-0 rx2s-rx0s receive time slot 16 spare bits select: bits rx2s-rx0s correspond to the spare bits x2-x0 in bit positions 8, 7 and 5 in time slot 16 of frame 0 in the multiframe (see table following figure 53). when a bit is set to 1, the corresponding spare bit received in time slot 16 is sent to the receive signaling highway via a buffer. when set to 0, the receive spare bit in the multiframe is disabled from being written into the buffer, and the value sitting in the buffer is frozen. the value of the bit in the buffer may be rewritten by the microprocessor for sending to the receive signaling highway. the buffer location is x80h. 1e0 - ch 1 2e0 - ch 2 3e0 - ch 3 4e0 - ch 4 7-1 rde7-rde1 receive time slot enable for time slots 7-1: when a bit in this regis- ter is set to 1, the corresponding received time slot is written into the slip buffer. the time slot is then read from the slip buffer for the receive data highway. when a bit in this register is written with a 0, the corresponding time slot will not be written into the slip buffer. instead, the microproces- sor writes the value of the time slot into the slip buffer and this value will be read from the slip buffer for the receive data highway. bit 7 is assigned to receive time slot 7. the slip buffers are located in registers x47h-x41h (frame 1) and x67h-x61h (frame 2). 0 reserved reserved : set to 0. 1e1 - ch 1 2e1 - ch 2 3e1 - ch 3 4e1 - ch 4 7-0 rde15-rde8 receive time slot enable for time slots 15-8: when a bit in this reg- ister is set to 1, the corresponding received time slot is written into the slip buffer. the time slot is then read from the slip buffer for the receive data highway. when a bit in this register is written with a 0, the corre- sponding time slot will not be written into the slip buffer. instead, the microprocessor writes the value of the time slot into the slip buffer and this value will be read from the slip buffer for the receive data highway. bit 7 is assigned to receive time slot 15. the slip buffers are located in registers x4fh-x48h (frame 1) and x6fh-x68h (frame 2). 1e2 - ch 1 2e2 - ch 2 3e2 - ch 3 4e2 - ch 4 7-0 rde23-rde16 receive time slot enable for time slots 23-16: when a bit in this register is set to 1, the corresponding received time slot is written into the slip buffer. the time slot is then read from the slip buffer for the receive data highway. when a bit in this register is written with a 0, the corresponding time slot will not be written into the slip buffer. instead, the microprocessor writes the value of the time slot into the slip buffer and this value will be read from the slip buffer for the receive data high- way. bit 7 is assigned to receive time slot 23. the slip buffers are located in registers x57h-x50h (frame 1) and x77h-x70h (frame 2). 1e3 - ch 1 2e3 - ch 2 3e3 - ch 3 4e3 - ch 4 7-0 rde31-rde24 receive time slot enable for time slots 31-24: when a bit in this register is set to 1, the corresponding received time slot is written into the slip buffer. the time slot is then read from the slip buffer for the receive data highway. when a bit in this register is written with a 0, the corresponding time slot will not be written into the slip buffer. instead, the microprocessor writes the value of the time slot into the slip buffer and this value will be read from the slip buffer for the receive data high- way. bit 7 is assigned to receive time slot 31. the slip buffers are located in registers x5fh-x58h (frame 1) and x7fh-x78h (frame 2). address bit symbol description -163 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet receive time slot registers the bits in these read/write registers are the receive time slots from the e1 frame format that are present in the two-frame slip buffer, when enabled. please note that, on loss of frame alignment, the states present in the slip buffer will be frozen to the states existing prior to the loss of frame alignment. address bit symbol description 140 - ch 1 240 - ch 2 340 - ch 3 440 - ch 4 7-0 rfas receive time slot 0 fas buffer: the time slot bits for time slot 0 in frames carrying the frame alignment pattern (fas, frame 1) are written into this location from the line. when control bit rsis (bit 7) in register x2ah, is written with a 0, the state of the international bit from the line cannot be written into the buffer, and the buffer value is frozen. the microprocessor can now write the value of the inter- national bit for receive time slot 0 to the system. the other bits represent the frame alignment sequence in time slot 0. 141-15f - ch 1 241-25f - ch 2 341-35f - ch 3 441-45f - ch 4 7-0 rts1-rts31 receive time slots 1-31: register locations x41h-x5fh repre- sent frame 1 in the two-frame slip buffer for the data highway. the register locations for a time slot are enabled when the correspond- ing receive time slot enable bits (rde1-rde31) in registers xe0h, xe1h, xe2h and xe3h are written with 1. when one or more con- trol bits in xe1h-xe3h are written with a 0, the corresponding receive time slot is disabled from being written into the buffer loca- tion, and the corresponding values in the two buffer locations are frozen. the microprocessor can now write an idle or service code to the corresponding buffer location. note: both frame locations in the slip buffer must be written for a time slot (see x61h to x7fh below). 160 - ch 1 260 - ch 2 360 - ch 3 460 - ch 4 7-0 rnfas receive time slot 0 nfas buffer: the time slot 0 bits for frames not carrying the frame alignment pattern (nfas, frame 2) are written into this location from the line. when control bit rsis (bit 7) and rsa4s-rsa8s (bits 4-0) in register x2ah are set to 0, the states of the corresponding international bit and national bits from the line cannot be written into the buffer, and the correspond- ing buffer value is frozen. the microprocessor can now write the value of the corresponding international bit and national bits for receive time slot 0 to the system. 161-17f - ch 1 261-27f - ch 2 361-37f - ch 3 461-47f - ch 4 7-0 rts1-rts31 receive time slots 1-31: register locations x61h-x7fh repre- sent frame 2 in the two-frame slip buffer for the data highway. the register locations for a time slot are enabled when the correspond- ing receive time slot enable bits (rde1-rde31) in registers xe0h, xe1h, xe2h and xe3h are written with 1. when one or more con- trol bits in xe1h-xe3h are written with a 0, the corresponding receive time slot is disabled from being written into the buffer loca- tion, and the corresponding values in the two buffer locations are frozen. the microprocessor can now write an idle or service code to the corresponding buffer location. note: both frame locations in the slip buffer must be written for a time slot (see x41h-x5fh above). -164 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet transmit time slot control registers the control bits in the following read/write registers are used to enable or disable (freeze) the transmit slip buffer locations for receiving input from the system highway, and to allow the microprocessor to write in service codes and idle codes. address bit symbol description 12c - ch 1 22c - ch 2 32c - ch 3 42c - ch 4 7tsis transmit international bits (si) select: this bit is enabled when the crc framing mode bits crcmd1 and crcmd0 (bits 2 and 1) in regis- ter x04h are equal to 01. when set to 1, the two international bits for frames 1 and 2 in time slot 0 from the signaling highway are sent as the transmit bits via a buffer. when set to 0, the transmit international bits are disabled from being written into the buffer, and the value sitting in the buffer is frozen. the value of these bits in the buffer may be rewrit- ten by the microprocessor for sending to the line. the buffer locations are registers x90h (fas, frame 1) and xb0h (nfas, frame 2). 6-5 reserved reserved: set to 0. 4-0 tsa4s-tsa8s transmit national bits (sa4-sa8) select: bit 4 corresponds to the transmit sa4 bit in time slot 0 of nfas frames. when a bit is set to 1, the corresponding transmit national bit of frame 2 received in time slot 0 on the transmit signaling highway is transmitted via a buffer when con- trol bit bnal (bit 1) in the framer configuration register x01h is a 1. when a bit is set to 0, the corresponding transmit national bit from the signaling highway is disabled from being written into the buffer, and the value sitting in the buffer is frozen. the value of the bit in the buffer may be rewritten by the microprocessor for sending to the line. the buffer location is register xb0h. 12d - ch 1 22d - ch 2 32d - ch 3 42d - ch 4 7-3 reserved reserved: set to 0. 2-0 tx2s-tx0s transmit time slot 16 spare bits select: bits tx2s-tx0s corre- spond to the spare bits x2-x0 in bit positions 8, 7 and 5 in time slot 16 of frame 0 in the multiframe (see table following figure 53). when a bit is set to 1, the corresponding spare bit in time slot 16 from the transmit signaling highway is transmitted via a buffer. when set to 0, the transmit spare bit is disabled from being written into the buffer, and the value sit- ting in the buffer is frozen. the value of the bit in the buffer may be rewritten by the microprocessor for sending to the line. the buffer loca- tion is xd0h. this function operates only in transmission mode. 1e4 - ch 1 2e4 - ch 2 3e4 - ch 3 4e4 - ch 4 7-1 tde7-tde1 transmit time slot enable for time slots 7-1: when a bit in this reg- ister is set to 1, the corresponding transmit time slot from the transmit data highway is written into the slip buffer. the time slot is then read from the slip buffer for the transmit line. when a bit in this register is writ- ten with a 0, the corresponding time slot from the data highway will not be written into the slip buffer. instead, the microprocessor writes the value of the time slot into the slip buffer and this value will be read from the slip buffer for the transmit line. bit 7 is assigned to transmit time slot 7. the slip buffers are located in registers x97h-x91h (frame 1) and xb7h-xb1h (frame 2). 0 reserved reserved : set to 0. -165 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet 1e5 - ch 1 2e5 - ch 2 3e5 - ch 3 4e5 - ch 4 7-0 tde15-tde8 transmit time slot enable for time slots 15-8: when a bit in this register is set to 1, the corresponding transmit time slot from the trans- mit data highway is written into the slip buffer. the time slot is then read from the slip buffer for the transmit line. when a bit in this register is writ- ten with a 0, the corresponding time slot from the data highway will not be written into the slip buffer. instead, the microprocessor writes the value of the time slot into the slip buffer and this value will be read from the slip buffer for the transmit line. bit 7 is assigned to transmit time slot 15. the slip buffers are located in registers x9fh-x98h (frame 1) and xbfh-xb8h (frame 2). 1e6 - ch 1 2e6 - ch 2 3e6 - ch 3 4e6 - ch 4 7-0 tde23-tde16 transmit time slot enable for time slots 23-16: when a bit in this register is set to 1, the corresponding transmit time slot from the trans- mit data highway is written into the slip buffer. the time slot is then read from the slip buffer for the transmit line. when a bit in this register is writ- ten with a 0, the corresponding time slot from the data highway will not be written into the slip buffer. instead, the microprocessor writes the value of the time slot into the slip buffer and this value will be read from the slip buffer for the transmit line. bit 7 is assigned to transmit time slot 23. the slip buffers are located in registers xa7h-xa0h (frame 1) and xc7h-xc0h (frame 2). 1e7 - ch 1 2e7 - ch 2 3e7 - ch 3 4e7 - ch 4 7-0 tde31-tde24 transmit time slot enable for time slots 31-24: when a bit in this register is set to 1, the corresponding transmit time slot from the trans- mit data highway is written into the slip buffer. the time slot is then read from the slip buffer for the transmit line. when a bit in this register is writ- ten with a 0, the corresponding time slot from the data highway will not be written into the slip buffer. instead, the microprocessor writes the value of the time slot into the slip buffer and this value will be read from the slip buffer for the transmit line. bit 7 is assigned to transmit time slot 31. the slip buffers are located in registers xafh-xa8h (frame 1) and xcfh-xc8h (frame 2). address bit symbol description -166 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet transmit time slot registers the bits in these read/write registers are the transmit time slots from the e1 frame format that are present in the two-frame slip buffer, when enabled. address bit symbol description 190 - ch 1 290 - ch 2 390 - ch 3 490 - ch 4 7-0 tfas transmit time slot 0 fas buffer: the time slot bits for time slot 0 in frames carrying the frame alignment pattern (fas, frame 1) are written into this location from the signaling highway in any mode. when control bit tsis (bit 7) in register x2ch is written with a 0, the state of the international bit from the system interface (sig- naling highway) cannot be written into the buffer and the buffer value is frozen. the microprocessor can now write the value of the international bit for transmit time slot 0 that will be sent to the line. 191-1af - ch 1 291-2af - ch 2 391-3af - ch 3 491-4af - ch 4 7-0 tts1-tts31 transmit time slots 1-31: register locations x91h-xafh repre- sent frame 1 in the two-frame slip buffer from the data highway. the register locations for a time slot are enabled when the corre- sponding transmit time slot enable bits (tde1-tde31) in registers xe4h, xe5h, xe6h and xe7h are written with 1. when one or more control bits in xe4h-xe7h are written with a 0, the corre- sponding transmit time slot is disabled from being written into the buffer location, and the corresponding values in the two buffer loca- tions are frozen. the microprocessor can now write an idle or ser- vice code to the corresponding buffer location. note: both frame locations in the slip buffer must be written for a time slot (see xb1h-xcfh below). 1b0 - ch 1 2b0 - ch 2 3b0 - ch 3 4b0 - ch 4 7-0 tnfas transmit time slot 0 nfas buffer: the time slot bits for time slot 0 in frames not carrying the frame alignment pattern (nfas, frame 2) are written into this location from the signaling highway in any mode. when control bit tsis (bit 7) and tsa4s-tsa8s (bits 4- 0) in register x2ch are set to 0, the states of the corresponding international bit and national bits from the system interface (signal- ing highway) cannot be written into the buffer, and the correspond- ing buffer value is frozen. the microprocessor can now write the values of the corresponding international bit and national bits for transmit time slot 0 that will be sent to the line. this write opera- tion must be verified by reading the location after more than 10 microseconds has elapsed. if this value is not the same as written, then repeat write/read operation until it is correct. 1b1-1cf - ch 1 2b1-2cf - ch 2 3b1-3cf - ch 3 4b1-4cf - ch 4 7-0 tts1-tts31 transmit time slots 1-31: register locations xb1h-xcfh repre- sent frame 2 in the two-frame slip buffer from the data highway. the register locations for a time slot are enabled when the corre- sponding transmit time slot enable bits (tde1-tde31) in registers xe4h, xe5h, xe6h, and xe7h are written with 1. when one or more control bits in xe4h-xe7h are written with a 0, the corre- sponding transmit time slot is disabled from being written into the buffer location, and the corresponding values in the two buffer loca- tions are frozen. the microprocessor can now write an idle or ser- vice code to the corresponding buffer location. note: both locations in the slip buffer must be written for a time slot (see x91h-xafh above). -167 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet signaling control registers the bits in the following read/write registers control both the receive and transmit signaling buffer locations for telephone channels 1 through 30. please note that the signaling information for telephone channel 1 is carried in time slot 1, and for telephone channel 30 in time slot 31. time slot 16 is used for a signaling channel, not a telephone channel. address bit symbol description 1e8 - ch 1 2e8 - ch 2 3e8 - ch 3 4e8 - ch 4 7-0 se8-se1 signaling enable for channels 8-1: when a bit in this register is set to 1, the transmit and receive signaling bits for the corresponding tele- phone channel are enabled. the abcd signaling bits are written into the transmit and receive signaling buffers from the transmit signaling highway and the receive line, and are inserted into the transmit line and receive signaling highway. when set to 0, the signaling states in both the transmit and receive signaling buffers are frozen. the ability to inter- nally write the signaling bits from the signaling highway and line into the transmit and receive signaling buffers is disabled. this enables the microprocessor to write the signaling states into the transmit and receive signaling registers. bit 7 is the enable bit for channel 8. signal- ing information for telephone channel c is carried in time slot c. 1e9 - ch 1 2e9 - ch 2 3e9 - ch 3 4e9 - ch 4 7-0 se16-se9 signaling enable for channels 16-9: when a bit in this register is set to 1, the transmit and receive signaling bits for the corresponding tele- phone channel are enabled. the abcd signaling bits are written into the transmit and receive signaling buffers from the transmit signaling highway and the receive line, and are inserted into the transmit line and receive signaling highway. when set to 0, the signaling states in both the transmit and receive signaling buffers are frozen. the ability to inter- nally write the signaling bits from the signaling highway and line into the transmit and receive signaling buffers is disabled. this enables the microprocessor to write the signaling states into the transmit and receive signaling registers. bit 7 is the enable bit for channel 16. signal- ing information for telephone channel c is carried in time slot c, except for channel 16, which is carried in time slot 17. 1ea - ch 1 2ea - ch 2 3ea - ch 3 4ea - ch 4 7-0 se24-se17 signaling enable for channels 24-17: when a bit in this register is set to 1, the transmit and receive signaling bits for the corresponding tele- phone channel are enabled. the abcd signaling bits are written into the transmit and receive signaling buffers from the transmit signaling highway and the receive line, and are inserted into the transmit line and receive signaling highway. when set to 0, the signaling states in both the transmit and receive signaling buffers are frozen. the ability to inter- nally write the signaling bits from the signaling highway and line into the transmit and receive signaling buffers is disabled. this enables the microprocessor to write the signaling states into the transmit and receive signaling registers. bit 7 is the enable bit for channel 24. signal- ing information for telephone channel c is carried in time slot c+1. -168 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet receive and transmit signaling registers the following read/write register locations contain the abcd signaling states associated with each of the tele- phone channels carried in time slots 1 through 31. when the signaling states for a channel are frozen, the microprocessor can write a new signaling state using the following registers. 1eb - ch 1 2eb - ch 2 3eb - ch 3 4eb - ch 4 7-6 reserved reserved: set to 0. 5-0 se30-se25 signaling enable for channels 30-25: when a bit in this register is set to 1, the transmit and receive signaling bits for the corresponding tele- phone channel are enabled. the abcd signaling bits are written into the transmit and receive signaling buffers from the transmit signaling highway and the receive line, and are inserted into the transmit line and receive signaling highway. when set to 0, the signaling states in both the transmit and receive signaling buffers are frozen. the ability to inter- nally write the signaling bits from the signaling highway and line into the transmit and receive signaling buffers is disabled. this enables the microprocessor to write the signaling states into the transmit and receive signaling registers. bit 5 is the enable bit for channel 30. signal- ing information for telephone channel c is carried in time slot c+1. address bit symbol description 180 - ch 1 280 - ch 2 380 - ch 3 480 - ch 4 7-4 rsigmas received signaling multiframe alignment signal: the bits in this register contain the states of the received multiframe alignment pattern (time slot 16 bits 1-4 in frame 0) in the receive signaling buffer. this pattern is normally 0000. bit 7 is received bit 1. 3-0 rx0, ry, rx1, rx2 received signaling spare bits and remote alarm bit: bits 3, 1 and 0 in this register contain the states of the received x0, x1, x2 bits (spare bits) in time slot 16, which correspond to bits 5, 7, and 8 in frame 0 of the multiframe. the ry bit (bit 2) is defined as the loss of multiframe indication bit and is carried in bit 6 in frame 0 of the multiframe. 181 - ch 1 281 - ch 2 381 - ch 3 481 - ch 4 7-4 3-0 ra1-rd1 ra16-rd16 receive a1-d1 and a16-d16 signaling bits: the signaling bits in this register are the states of the received a1 to d1 bits and the a16 to d16 bits in the receive signaling buffer. the bits correspond to the abcd sig- naling bits carried in time slot 16 for channels 1 (time slot 1) and 16 (time slot 17). bit 7 is the a1 signaling bit value. please note that a receive signaling state is written into the signaling buffer when the corre- sponding channel enable bit sec is written with a 1 (where c is the channel number, from 1 to 30). when the corresponding enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position in this register represents the last value written into the buffer. the microprocessor can write the state of the outgoing signaling bits for channels 1 and 16 in this register. address bit symbol description -169 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet 182 - ch 1 282 - ch 2 382 - ch 3 482 - ch 4 7-4 3-0 ra2-rd2 ra17-rd17 receive a2-d2 and a17-d17 signaling bits: the signaling bits in this register are the states of the received a2 to d2 bits and the a17 to d17 bits in the receive signaling buffer. the bits correspond to the abcd sig- naling bits carried in time slot 16 for channels 2 (time slot 2) and 17 (time slot 18). bit 7 is the a2 signaling bit value. please note that a receive signaling state is written into the signaling buffer when the corre- sponding channel enable bit sec is written with a 1. when the corre- sponding enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position represents the last value written into the buffer. the microprocessor can write the state of the outgoing signaling bits for channels 2 and 17 in this register. 183 - ch 1 283 - ch 2 383 - ch 3 483 - ch 4 7-4 3-0 ra3-rd3 ra18-rd18 receive a3-d3 and a18-d18 signaling bits: the signaling bits in this register are the states of the received a3 to d3 bits and the a18 to d18 bits in the receive signaling buffer. the bits correspond to the abcd sig- naling bits carried in time slot 16 for channels 3 (time slot 3) and 18 (time slot 19). bit 7 is the a3 signaling bit value. please note that a receive signaling state is written into the signaling buffer when the corre- sponding channel enable bit sec is written with a 1. when the corre- sponding enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position represents the last value written into the buffer. the microprocessor can write the state of the outgoing signaling bits for channels 3 and 18 in this register. 184 - ch 1 284 - ch 2 384 - ch 3 484 - ch 4 7-4 3-0 ra4-rd4 ra19-rd19 receive a4-d4 and a19-d19 signaling bits: the signaling bits in this register are the states of the received a4 to d4 bits and the a19 to d19 bits in the receive signaling buffer. the bits correspond to the abcd sig- naling bits carried in time slot 16 for channels 4 (time slot 4) and 19 (time slot 20). bit 7 is the a4 signaling bit value. please note that a receive signaling state is written into the signaling buffer when the corre- sponding channel enable bit sec is written with a 1. when the corre- sponding enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position represents the last value written into the buffer. the microprocessor can write the state of the outgoing signaling bits for channels 4 and 19 in this register. 185 - ch 1 285 - ch 2 385 - ch 3 485 - ch 4 7-4 3-0 ra5-rd5 ra20-rd20 receive a5-d5 and a20-d20 signaling bits: the signaling bits in this register are the states of the received a5 to d5 bits and the a20 to d20 bits in the receive signaling buffer. the bits correspond to the abcd sig- naling bits carried in time slot 16 for channels 5 (time slot 5) and 20 (time slot 21). bit 7 is the a5 signaling bit value. please note that a receive signaling state is written into the signaling buffer when the corre- sponding channel enable bit sec is written with a 1. when the corre- sponding enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position represents the last value written into the buffer. the microprocessor can write the state of the outgoing signaling bits for channels 5 and 20 in this register. address bit symbol description -170 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet 186 - ch 1 286 - ch 2 386 - ch 3 486 - ch 4 7-4 3-0 ra6-rd6 ra21-rd21 receive a6-d6 and a21-d21 signaling bits: the signaling bits in this register are the states of the received a6 to d6 bits and the a21 to d21 bits in the receive signaling buffer. the bits correspond to the abcd sig- naling bits carried in time slot 16 for channels 6 (time slot 6) and 21 (time slot 22). bit 7 is the a6 signaling bit value. please note that a receive signaling state is written into the signaling buffer when the corre- sponding enable bit sec is written with a 1. when the corresponding channel enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position represents the last value written into the buffer. the microprocessor can write the state of the outgoing signaling bits for channels 6 and 21 in this register. 187 - ch 1 287 - ch 2 387 - ch 3 487 - ch 4 7-4 3-0 ra7-rd7 ra22-rd22 receive a7-d7 and a22-d22 signaling bits: the signaling bits in this register are the states of the received a7 to d7 bits and the a22 to d22 bits in the receive signaling buffer. the bits correspond to the abcd sig- naling bits carried in time slot 16 for channels 7 (time slot 7) and 22 (time slot 23). bit 7 is the a7 signaling bit value. please note that a receive signaling state is written into the signaling buffer when the corre- sponding enable bit sec is written with a 1. when the corresponding channel enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position represents the last value written into the buffer. the microprocessor can write the state of the outgoing signaling bits for channels 7 and 22 in this register. 188 - ch 1 288 - ch 2 388 - ch 3 488 - ch 4 7-4 3-0 ra8-rd8 ra23-rd23 receive a8-d8 and a23-d23 signaling bits: the signaling bits in this register are the states of the received a8 to d8 bits and the a23 to d23 bits in the receive signaling buffer. the bits correspond to the abcd sig- naling bits carried in time slot 16 for channels 8 (time slot 8) and 23 (time slot 24). bit 7 is the a8 signaling bit value. please note that a receive signaling state is written into the signaling buffer when the corre- sponding enable bit sec is written with a 1. when the corresponding channel enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position represents the last value written into the buffer. the microprocessor can write the state of the outgoing signaling bits for channels 8 and 23 in this register. 189 - ch 1 289 - ch 2 389 - ch 3 489 - ch 4 7-4 3-0 ra9-rd9 ra24-rd24 receive a9-d9 and a24-d24 signaling bits: the signaling bits in this register are the states of the received a9 to d9 bits and the a24 to d24 bits in the receive signaling buffer. the bits correspond to the abcd sig- naling bits carried in time slot 16 for channels 9 (time slot 9) and 24 (time slot 25). bit 7 is the a9 signaling bit value. please note that a receive signaling state is written into the signaling buffer when the corre- sponding enable bit sec is written with a 1. when the corresponding channel enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position represents the last value written into the buffer. the microprocessor can write the state of the outgoing signaling bits for channels 9 and 24 in this register. address bit symbol description -171 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet 18a - ch 1 28a - ch 2 38a - ch 3 48a - ch 4 7-4 3-0 ra10-rd10 ra25-rd25 receive a10-d10 and a25-d25 signaling bits: the signaling bits in this register are the states of the received a10 to d10 bits and the a25 to d25 bits in the receive signaling buffer. the bits correspond to the abcd signaling bits carried in time slot 16 for channels 10 (time slot 10) and 25 (time slot 26). bit 7 is the a10 signaling bit value. please note that a receive signaling state is written into the signaling buffer when the corresponding channel enable bit sec is written with a 1. when the corresponding enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position represents the last value writ- ten into the buffer. the microprocessor can write the state of the outgo- ing signaling bits for channels 10 and 25 in this register. 18b - ch 1 28b - ch 2 38b - ch 3 48b - ch 4 7-4 3-0 ra11-rd11 ra26-rd26 receive a11-d11 and a26-d26 signaling bits: the signaling bits in this register are the states of the received a11 to d11 bits and the a26 to d26 bits in the receive signaling buffer. the bits correspond to the abcd signaling bits carried in time slot 16 for channels 11 (time slot 11) and 26 (time slot 27). bit 7 is the a11 signaling bit value. please note that a receive signaling state is written into the signaling buffer when the corresponding channel enable bit sec is written with a 1. when the corresponding enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position represents the last value writ- ten into the buffer. the microprocessor can write the state of the outgo- ing signaling bits for channels 11 and 26 in this register. 18c - ch 1 28c - ch 2 38c - ch 3 48c - ch 4 7-4 3-0 ra12-rd12 ra27-rd27 receive a12-d12 and a27-d27 signaling bits: the signaling bits in this register are the states of the received a12 to d12 bits and the a27 to d27 bits in the receive signaling buffer. the bits correspond to the abcd signaling bits carried in time slot 16 for channels 12 (time slot 12) and 27 (time slot 28). bit 7 is the a12 signaling bit value. please note that a receive signaling state is written into the signaling buffer when the corresponding channel enable bit sec is written with a 1. when the corresponding enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position represents the last value writ- ten into the buffer. the microprocessor can write the state of the outgo- ing signaling bits for channels 12 and 27 in this register. 18d - ch 1 28d - ch 2 38d - ch 3 48d - ch 4 7-4 3-0 ra13-rd13 ra28-rd28 receive a13-d13 and a28-d28 signaling bits: the signaling bits in this register are the states of the received a13 to d13 bits and the a28 to d28 bits in the receive signaling buffer. the bits correspond to the abcd signaling bits carried in time slot 16 for channels 13 (time slot 13) and 28 (time slot 29). bit 7 is the a13 signaling bit value. please note that a receive signaling state is written into the signaling buffer when the corresponding channel enable bit sec is written with a 1. when the corresponding enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position represents the last value writ- ten into the buffer. the microprocessor can write the state of the outgo- ing signaling bits for channels 13 and 28 in this register. address bit symbol description -172 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet 18e - ch 1 28e - ch 2 38e - ch 3 48e - ch 4 7-4 3-0 ra14-rd14 ra29-rd29 receive a14-d14 and a29-d29 signaling bits: the signaling bits in this register are the states of the received a14 to d14 bits and the a29 to d29 bits in the receive signaling buffer. the bits correspond to the abcd signaling bits carried in time slot 16 for channels 14 (time slot 14) and 29 (time slot 30). bit 7 is the a14 signaling bit value. please note that a receive signaling state is written into the signaling buffer when the corresponding channel enable bit sec is written with a 1. when the corresponding enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position represents the last value writ- ten into the buffer. the microprocessor can write the state of the outgo- ing signaling bits for channels 14 and 29 in this register. 18f - ch 1 28f - ch 2 38f - ch 3 48f - ch 4 7-4 3-0 ra15-rd15 ra30-rd30 receive a15-d15 and a30-d30 signaling bits: the signaling bits in this register are the states of the received a15 to d15 bits and the a30 to d30 bits in the receive signaling buffer. the bits correspond to the abcd signaling bits carried in time slot 16 for channels 15 (time slot 15) and 30 (time slot 31). bit 7 is the a15 signaling bit value. please note that a receive signaling state is written into the signaling buffer when the corresponding channel enable bit sec is written with a 1. when the corresponding enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position represents the last value writ- ten into the buffer. the microprocessor can write the state of the outgo- ing signaling bits for channels 15 and 30 in this register. 1d0 - ch 1 2d0 - ch 2 3d0 - ch 3 4d0 - ch 4 7-4 tsigmas transmit signaling multiframe alignment signal: the bits in this reg- ister contain the states of the transmit multiframe alignment pattern (time slot 16 bits 1-4 in frame 0) in the transmit signaling buffer. this pattern is normally 0000. bit 7 is transmitted bit 1. 3-0 tx0, ty, tx1, tx2 transmit signaling spare bits: bits 3, 1 and 0 in this register contain the states of the transmit x0, x1, x2 bits (spare bits) in time slot 16, which are carried in bits 5, 7, and 8 of frame 0 in the multiframe. the ty bit (bit 2) is defined as the loss of multiframe indication bit and is carried in bit 6 in frame 0 of the multiframe. the ty bit is not propagated from the signaling highway to the line in any modes. the tx bits are not propagated from the signaling highway to the line except when the framer is in any of the transmission modes (2 mbit/s, 8 mbit/s or 16 mbit/s). 1d1 - ch 1 2d1 - ch 2 3d1 - ch 3 4d1 - ch 4 7-4 3-0 ta 1 - t d 1 ta 1 6 - t d 1 6 transmit a1-d1 and a16-d16 signaling bits: the signaling bits in this register are the a1 to d1 and a16 to d16 signaling bits written into the signaling buffer from the transmit signaling highway. the bits corre- spond to the abcd signaling bits carried in time slot 16 for channels 1 (time slot 1) and 16 (time slot 17). bit 7 is the a1 signaling bit value. please note that a transmit signaling state is written into the signaling buffer when the corresponding channel enable bit sec is written with a 1. when the corresponding enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position represents the last value written into the buffer. the microprocessor can write the state of the transmitted signaling bits that correspond to channels 1 and 16 in this register. address bit symbol description -173 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet 1d2 - ch 1 2d2 - ch 2 3d2 - ch 3 4d2 - ch 4 7-4 3-0 ta 2 - t d 2 ta 1 7 - t d 1 7 transmit a2-d2 and a17-d17 signaling bits: the signaling bits in this register are the a2 to d2 and a17 to d17 signaling bits written into the signaling buffer from the transmit signaling highway. the bits corre- spond to the abcd signaling bits carried in time slot 16 for channels 2 (time slot 2) and 17 (time slot 18). bit 7 is the a2 signaling bit value. please note that a transmit signaling state is written into the signaling buffer when the corresponding enable bit sec is written with a 1. when the corresponding channel enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position represents the last value written into the buffer. the microprocessor can write the state of the transmitted signaling bits that correspond to channels 2 and 17 in this register. 1d3 - ch 1 2d3 - ch 2 3d3 - ch 3 4d3 - ch 4 7-4 3-0 ta 3 - t d 3 ta 1 8 - t d 1 8 transmit a3-d3 and a18-d18 signaling bits: the signaling bits in this register are the a3 to d3 and a18 to d18 signaling bits written into the signaling buffer from the transmit signaling highway. the bits corre- spond to the abcd signaling bits carried in time slot 16 for channels 3 (time slot 3) and 18 (time slot 19). bit 7 is the a3 signaling bit value. please note that a transmit signaling state is written into the signaling buffer when the corresponding channel enable bit sec is written with a 1. when the corresponding enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position represents the last value written into the buffer. the microprocessor can write the state of the transmitted signaling bits that correspond to channels 3 and 18 in this register. 1d4 - ch 1 2d4 - ch 2 3d4 - ch 3 4d4 - ch 4 7-4 3-0 ta 4 - t d 4 ta 1 9 - t d 1 9 transmit a4-d4 and a19-d19 signaling bits: the signaling bits in this register are the a4 to d4 and a19 to d19 signaling bits written into the signaling buffer from the transmit signaling highway. the bits corre- spond to the abcd signaling bits carried in time slot 16 for channels 4 (time slot 4) and 19 (time slot 20). bit 7 is the a4 signaling bit value. please note that a transmit signaling state is written into the signaling buffer when the corresponding channel enable bit sec is written with a 1. when the corresponding enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position represents the last value written into the buffer. the microprocessor can write the state of the transmitted signaling bits that correspond to channels 4 and 19 in this register. 1d5 - ch 1 2d5 - ch 2 3d5 - ch 3 4d5 - ch 4 7-4 3-0 ta 5 - t d 5 ta 2 0 - t d 2 0 transmit a5-d5 and a20-d20 signaling bits: the signaling bits in this register are the a5 to d5 and a20 to d20 signaling bits written into the signaling buffer from the transmit signaling highway. the bits corre- spond to the abcd signaling bits carried in time slot 16 for channels 5 (time slot 5) and 20 (time slot 21). bit 7 is the a5 signaling bit value. please note that a transmit signaling state is written into the signaling buffer when the corresponding channel enable bit sec is written with a 1. when the corresponding enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position represents the last value written into the buffer. the microprocessor can write the state of the transmitted signaling bits that correspond to channels 5 and 20 in this register. address bit symbol description -174 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet 1d6 - ch 1 2d6 - ch 2 3d6 - ch 3 4d6 - ch 4 7-4 3-0 ta 6 - t d 6 ta 2 1 - t d 2 1 transmit a6-d6 and a21-d21 signaling bits: the signaling bits in this register are the a6 to d6 and a21 to d21 signaling bits written into the signaling buffer from the transmit signaling highway. the bits corre- spond to the abcd signaling bits carried in time slot 16 for channels 6 (time slot 6) and 21 (time slot 22). bit 7 is the a6 signaling bit value. please note that a transmit signaling state is written into the signaling buffer when the corresponding channel enable bit sec is written with a 1. when the corresponding enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position represents the last value written into the buffer. the microprocessor can write the state of the transmitted signaling bits that correspond to channels 6 and 21 in this register. 1d7 - ch 1 2d7 - ch 2 3d7 - ch 3 4d7 - ch 4 7-4 3-0 ta 7 - t d 7 ta 2 2 - t d 2 2 transmit a7-d7 and a22-d22 signaling bits: the signaling bits in this register are the a7 to d7 and a22 to d22 signaling bits written into the signaling buffer from the transmit signaling highway. the bits corre- spond to the abcd signaling bits carried in time slot 16 for channels 7 (time slot 7) and 22 (time slot 23). bit 7 is the a7 signaling bit value. please note that a transmit signaling state is written into the signaling buffer when the corresponding channel enable bit sec is written with a 1. when the corresponding enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position represents the last value written into the buffer. the microprocessor can write the state of the transmitted signaling bits that correspond to channels 7 and 22 in this register. 1d8 - ch 1 2d8 - ch 2 3d8 - ch 3 4d8 - ch 4 7-4 3-0 ta 8 - t d 8 ta 2 3 - t d 2 3 transmit a8-d8 and a23-d23 signaling bits: the signaling bits in this register are the a8 to d8 and a23 to d23 signaling bits written into the signaling buffer from the transmit signaling highway. the bits corre- spond to the abcd signaling bits carried in time slot 16 for channels 8 (time slot 8) and 23 (time slot 24). bit 7 is the a8 signaling bit value. please note that a transmit signaling state is written into the signaling buffer when the corresponding channel enable bit sec is written with a 1. when the corresponding enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position represents the last value written into the buffer. the microprocessor can write the state of the transmitted signaling bits that correspond to channels 8 and 23 in this register. 1d9 - ch 1 2d9 - ch 2 3d9 - ch 3 4d9 - ch 4 7-4 3-0 ta 9 - t d 9 ta 2 4 - t d 2 4 transmit a9-d9 and a24-d24 signaling bits: the signaling bits in this register are the a9 to d9 and a24 to d24 signaling bits written into the signaling buffer from the transmit signaling highway. the bits corre- spond to the abcd signaling bits carried in time slot 16 for channels 9 (time slot 9) and 24 (time slot 25). bit 7 is the a9 signaling bit value. please note that a transmit signaling state is written into the signaling buffer when the corresponding channel enable bit sec is written with a 1. when the corresponding enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position represents the last value written into the buffer. the microprocessor can write the state of the transmitted signaling bits that correspond to channels 9 and 24 in this register. address bit symbol description -175 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet 1da - ch 1 2da - ch 2 3da - ch 3 4da - ch 4 7-4 3-0 ta 1 0 - t d 1 0 ta 2 5 - t d 2 5 transmit a10-d10 and a25-d25 signaling bits: the signaling bits in this register are the a10 to d10 and a25 to d25 signaling bits written into the signaling buffer from the transmit signaling highway. the bits correspond to the abcd signaling bits carried in time slot 16 for chan- nels 10 (time slot 10) and 25 (time slot 26). bit 7 is the a10 signaling bit value. please note that a transmit signaling state is written into the signaling buffer when the corresponding channel enable bit sec is writ- ten with a 1. when the corresponding enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position represents the last value written into the buffer. the microprocessor can write the state of the transmitted signaling bits that correspond to channels 10 and 25 in this register. 1db - ch 1 2db - ch 2 3db - ch 3 4db - ch 4 7-4 3-0 ta 1 1 - t d 1 1 ta 2 6 - t d 2 6 transmit a11-d11 and a26-d26 signaling bits: the signaling bits in this register are the a11 to d11 and a26 to d26 signaling bits written into the signaling buffer from the transmit signaling highway. the bits correspond to the abcd signaling bits carried in time slot 16 for chan- nels 11 (time slot 11) and 26 (time slot 27). bit 7 is the a11 signaling bit value. please note that a transmit signaling state is written into the signaling buffer when the corresponding channel enable bit sec is writ- ten with a 1. when the corresponding enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position represents the last value written into the buffer. the microprocessor can write the state of the transmitted signaling bits that correspond to channels 11 and 26 in this register. 1dc - ch 1 2dc - ch 2 3dc - ch 3 4dc - ch 4 7-4 3-0 ta 1 2 - t d 1 2 ta 2 7 - t d 2 7 transmit a12-d12 and a27-d27 signaling bits: the signaling bits in this register are the a12 to d12 and a27 to d27 signaling bits written into the signaling buffer from the transmit signaling highway. the bits correspond to the abcd signaling bits carried in time slot 16 for chan- nels 12 (time slot 12) and 27 (time slot 28). bit 7 is the a12 signaling bit value. please note that a transmit signaling state is written into the signaling buffer when the corresponding channel enable bit sec is writ- ten with a 1. when the corresponding enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position represents the last value written into the buffer. the microprocessor can write the state of the transmitted signaling bits that correspond to channels 12 and 27 in this register. 1dd - ch 1 2dd - ch 2 3dd - ch 3 4dd - ch 4 7-4 3-0 ta 1 3 - t d 1 3 ta 2 8 - t d 2 8 transmit a13-d13 and a28-d28 signaling bits: the signaling bits in this register are the a13 to d13 and a28 to d28 signaling bits written into the signaling buffer from the transmit signaling highway. the bits correspond to the abcd signaling bits carried in time slot 16 for chan- nels 13 (time slot 13) and 28 (time slot 29). bit 7 is the a13 signaling bit value. please note that a transmit signaling state is written into the signaling buffer when the corresponding channel enable bit sec is writ- ten with a 1. when the corresponding enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position represents the last value written into the buffer. the microprocessor can write the state of the transmitted signaling bits that correspond to channels 13 and 28 in this register. address bit symbol description -176 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet hdlc link control registers the bits in the following read/write registers control the transmit and receive hdlc link that is carried in the sa bits (bits 4-8) of time slot 0 in nfas frames (frame 2). 1de - ch 1 2de - ch 2 3de - ch 3 4de - ch 4 7-4 3-0 ta 1 4 - t d 1 4 ta 2 9 - t d 2 9 transmit a14-d14 and a29-d29 signaling bits: the signaling bits in this register are the a14 to d14 and a29 to d29 signaling bits written into the signaling buffer from the transmit signaling highway. the bits correspond to the abcd signaling bits carried in time slot 16 for chan- nels 14 (time slot 14) and 29 (time slot 30). bit 7 is the a14 signaling bit value. please note that a transmit signaling state is written into the signaling buffer when the corresponding channel enable bit sec is writ- ten with a 1. when the corresponding enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position represents the last value written into the buffer. the microprocessor can write the state of the transmitted signaling bits that correspond to channels 14 and 29 in this register. 1df - ch 1 2df - ch 2 3df - ch 3 4df - ch 4 7-4 3-0 ta 1 5 - t d 1 5 ta 3 0 - t d 3 0 transmit a15-d15 and a30-d30 signaling bits: the signaling bits in this register are the a15 to d15 and a30 to d30 signaling bits written into the signaling buffer from the transmit signaling highway. the bits correspond to the abcd signaling bits carried in time slot 16 for chan- nels 15 (time slot 15) and 30 (time slot 31). bit 7 is the a15 signaling bit value. please note that a transmit signaling state is written into the signaling buffer when the corresponding channel enable bit sec is writ- ten with a 1. when the corresponding enable bit is written with a 0, a signaling freeze occurs, and the value read in a bit position represents the last value written into the buffer. the microprocessor can write the state of the transmitted signaling bits that correspond to channels 15 and 30 in this register. address bit symbol description 108 - ch 1 208 - ch 2 308 - ch 3 408 - ch 4 7ehr enable hdlc receiver: a 1 enables the hdlc receiver. after flag detection and zero bit destuffing the bytes are written into the receive hdlc fifo. a 0 disables the hdlc controller, clears the fifo, and dis- ables the hdlc receive interrupts. 6 eht enable hdlc transmitter: a 1 enables the hdlc transmitter. the transmitter will send flags when the transmit hdlc fifo is empty. the bytes are formatted into the message when the fifo has bytes present. a 0 disables the hdlc controller, clears the fifo, disables the hdlc transmit interrupts, but will continue to send flags as a fill in selected na- tional bits if control bits sa4-sa8 (bit 4-0) in register x0ch are set to a 1 unless bypassed by control bit bnal (bit 1) in register x01h is set to a1. 5 ta b transmit abort: when set to 1, the transmit hdlc controller will trans- mit the abort sequence (a zero followed by seven ones) after the next data byte. this is followed by clearing the transmit hdlc fifo, and sending continuous flags. 4eom transmit end of message flag: when set to 1, the transmit hdlc fifo contains the last byte in the message. when the fifo has emp- tied, the 16-bit crc is transmitted, and this followed by an interrupt. address bit symbol description -177 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet hdlc link transmit and receive data registers the first two registers are used for writing the transmit bytes into the 16-byte transmit fifo, and for reading the receive bytes from the receive fifo, for the hdlc message. register x18h indicates the number of bytes in the receive fifo. all registers are read/write. these registers are either read or written, not both, for normal operation. for these registers, a write operation may not be followed by a read operation unless at least 7 cycles of sysclk occur following the end of the last write cycle. 108 - ch 1 208 - ch 2 308 - ch 3 408 - ch 4 (cont.) 3 rhie receiver half full interrupt enable: rhie defines the function of the receive hdlc interrupt status bits rhis2-rhis0 (bits 7-5 of register x16h). when set to 1, the receive hdlc controller generates an inter- rupt when the receive hdlc fifo is half full, or at the end of the mes- sage. when set to 0, the hdlc controller generates an interrupt request only at the end of the message or when the fifo has overflowed. 2thie transmit half full interrupt enable: thie defines the function of the transmit hdlc interrupt status bit this (bit 4 of register x16h). when set to 1, the transmit hdlc controller generates an interrupt when the transmit hdlc fifo is half full, or at the end of the message. when set to 0, the hdlc controller generates an interrupt request only at the end of the message or when the fifo has underflowed. 1-0 reserved reserved: set to 0. 10c - ch 1 20c - ch 2 30c - ch 3 40c - ch 4 7-5 reserved reserved: set to 0. 4-0 sa4-sa8 enable sa bits: a 1 written to one or more bits selects the correspond- ing sa bit in time slot 0 of nfas frames (frame 2) to be included as part of the hdlc link. for example, a value of 11111 selects all five of the national bits sa4 through sa8 as the data link and provides a bandwidth of 5 x 4 = 20 kbit/s. address bit symbol description 10a - ch 1 20a - ch 2 30a - ch 3 40a - ch 4 7-0 thd7-thd0 hdlc transmit data: the byte written to this location is written to the transmit fifo. bit 0 corresponds to the first bit transmitted in the hdlc message byte. 117 - ch 1 217 - ch 2 317 - ch 3 417 - ch 4 7-0 rhd7-rhd0 hdlc receive data: a read cycle transfers one byte from the receive fifo into this location. bit 0 corresponds to the first bit received in the hdlc message byte. 118 - ch 1 218 - ch 2 318 - ch 3 418 - ch 4 7-5 reserved reserved: set to 0. 4-0 c4-c0 hdlc receive fifo depth : this register indicates the number of data bytes currently present in the hdlc receive fifo. the value read is in binary. bit 0 is the lsb value. for example, the value 00000 indicates that the fifo is empty, and the value 01111 indicates that there are 15 bytes present in the receive fifo. address bit symbol description -178 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet hdlc link status registers these registers are all read/write. the status bits in the x0e registers represent the latched status and inter- rupt request indications generated by the receive and transmit hdlc controllers and the fifos. the latched event bits are a result of a receive or transmit status indication or interrupt request in the hdlc link status register x16h. the bits latch on either the rising edge, the falling edge, or both edges of the current status or interrupt request event bits as defined by the rise/fall control bits (bits 6 and 5) in the global configuration register 006h. a latched bit causes a hardware interrupt indication when the corresponding mask bit in the hdlc link mask register x0fh is written with a 0. the status bits in register x16h represent the current (unlatched) status and interrupt request indications generated by the receive and transmit hdlc controllers and fifos. address bit symbol description 10e - ch 1 20e - ch 2 30e - ch 3 40e - ch 4 7-5 erhis2- erhis0 latched receive hdlc interrupt events: the latched bits in this loca- tion correspond to a receive hdlc interrupt status indication in bits 7-5 in register x16h. these bits are cleared by writing a 0 to any bit position that is set. a hardware interrupt is generated when any of these bits latches and the corresponding mask bit position in register x0fh is written with a 0. during normal message reception erhis0 does not get set at the start of message reception (rhis2 - rhis0 = 001). 4 ethis latched transmit hdlc interrupt event: the latched bit in this location corresponds to a transmit hdlc interrupt status indication in bit 4 in reg- ister x16h. this bit is cleared by writing a 0 to it. a hardware interrupt is generated when this bit latches and the corresponding mask bit position in register x0fh is written with a 0. 3-2 erxfs1- erxfs0 latched receive hdlc fifo status events: the latched bits in this location correspond to receive hdlc fifo status indications in bits 3-2 in x16h. these bits are cleared by writing a 0 to any bit position that is set. if not masked by the corresponding mask bit position in register x0fh, a hardware interrupt is generated when any of these bits latches. 1-0 etxfs1- etxfs0 latched transmit hdlc fifo status events: the latched bits in this location correspond to transmit hdlc fifo status indications in bits 1-0 in register x16h. these bits are cleared by writing a 0 to any bit position that is set. a hardware interrupt is generated when this bit latches and the corresponding mask bit position in register x0fh is written with a 0. 10f - ch 1 20f - ch 2 30f - ch 3 40f - ch 4 7-5 mrhis2- mrhis0 receive hdlc interrupt mask: when one or more bits are set to a 1, the latched receive hdlc interrupt event indications in corresponding bits 7-5 in register x0eh are masked from causing a hardware interrupt. for example, if 001 is written into this location, a start of message indication is masked from causing a hardware interrupt (see rhis2-rhis0). 4 mthis transmit hdlc interrupt mask: when set to 1, the latched transmit hdlc interrupt event indication corresponding to bit 4 in register x0eh is masked from causing a hardware interrupt (see this). 3-2 mrxfs1- mrxfs0 receive hdlc fifo status interrupt mask: when one or more bits are set to a 1, a latched receive hdlc fifo event indication in corresponding bits 3-2 in register x0eh is masked from causing a hardware interrupt. for example, if a 01 is written into this location, a half or more than half full indication is masked from causing a hardware interrupt (see rxfs1- rxfs0). -179 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet 10f - ch 1 20f - ch 2 30f - ch 3 40f - ch 4 (cont.) 1-0 mtxfs1- mtxfs0 transmit hdlc fifo status interrupt mask: when one or more bits are set to a 1, a latched transmit hdlc fifo status event that has taken place in corresponding bits 1-0 in register x0eh is masked from causing a hardware interrupt. for example, if a 01 is written into this location, a less than half full indication is masked from causing a hardware interrupt (see txfs1-txfs0). 116 - ch 1 216 - ch 2 316 - ch 3 416 - ch 4 7-5 rhis2-rhis0 receive hdlc interrupt status: the following table lists the various interrupt status indications for the receive hdlc message. condition 010 is additionally defined by control bit rhie (bit 3 of register x08h). rhis2 rhis1 rhis 0 rhie c ondition 0 0 0 x idle condition. 0 0 1 x start of message indication. 0 1 0 0 valid message received (crc checked ok) or fifo overflow. 0 1 0 1 valid message received (crc checked ok) or fifo needs servicing (e.g., half full). 0 1 1 x message received with a crc error. 1 x x x abort detected. x represents either value may be indicated. 4this transmit hdlc interrupt status: a 1 indicates that the transmit fifo needs servicing, either because the message is completed, or because the fifo is less than half full, as determined by control bit thie (bit 2 of register x08). 3-2 rxfs1-rxfs0 receive fifo status: the following table lists the various receive fifo status indications for the receive hdlc message. rxfs1 rxfs0 condition 0 0 normal. fifo less than half full. 0 1 fifo equal to or greater than half full. 10fifo full. 1 1 fifo overflowed (attempt to write to a full fifo). 1-0 txfs1-txfs0 transmit fifo status: the following table lists the various transmit fifo status indications for the transmit hdlc message. txfs1 txfs0 condition 0 0 normal. fifo equal to or greater than half full. 0 1 fifo less than half full. 1 0 fifo overflowed (attempt to write to a full fifo). 1 1 fifo underflowed (attempt to read an empty fifo). address bit symbol description -180 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet application diagram the diagram in figure 63 illustrates the use of the qe1f- plus device to provide framing and time slot access for a variety of e1 sources. direct control of most commercial line interface unit devices (lius) is provided. note that these applications require operating the qe1f- plus at v dd = +5.0 volt to comply with the +5.0 volt parts con- nected to the qe1f- plus . figure 63. some qe1f- plus TXC-03114 applications qe1m txc-04252 sot-3 txc-03003 syn155c txc-02302b sonet sts-3 32 ts +sig, clock & frame qe1f- plus TXC-03114 qe1f- plus TXC-03114 32 ts +sig, clock & frame } 64 kbit/s time slot applications (async) e123mux txc-03361 mrt txc-02050 e3 qe1f- plus TXC-03114 qe1f- plus TXC-03114 } 64 kbit/s time slot applications } 2.048 mbit/s mvip: ds0, sig, clk, data cross point (ds0) cross point (ds0) e1 liu liu e1 e1 e1 e1 e1 adma-e1 txc-04002b (2 units) qe1f- plus TXC-03114 e1 cdb txc-05150 liu liu e1 utopia/ fifo interface for cdb txc-05150 fractional e1 atm application -181 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet package information the qe1f- plus device is packaged in a 128-pin low profile plastic quad flat package suitable for surface mounting, as illustrated in figure 64. figure 64. qe1f- plus TXC-03114 128-pin low profile plastic quad flat package 102 65 39 38 1 128 103 64 pin #1 index 18.50 20.00 22.00 1.60 (max) 0.05 (min) 1.40 see detail ? a ? note: dimensions in millimeters 0.50 typ 0.18 (min) 0.27 (max) detail ? b ? detail ? c ? see details ? b ? and ? c ? 0.45 (min) 0 o -7 o detail ? a ? 14.00 16.00 12.50 0.10 (min) 0.20 (max) 0.75 (max) note: all linear dimensions are in millimeters and are nominal unless otherwise indicated. transwitch TXC-03114bilq note: this 128-pin low profile plastic quad flat package conforms to the jedec ms-026-bhb standard outline. -182 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet ordering information part number: TXC-03114bilq 128-pin low profile plastic quad flat package related products txc-02020/21, art/arte vlsi devices (advanced sts-1/ds3 receiver/transmit- ter). art performs the transmit and receive line interface functions required for trans- mission of sts-1 (51.840 mbit/s) and ds3 (44.736 mbit/s) signals across a coaxial interface. arte has the same functionality as art, plus expanded features. txc-02050, mrt multi-rate line interface device. the mrt directly interfaces with the e123mux device and provides the functions for terminating itu-t-specified 8448 kbit/s (e2) and 34368 kbit/s (e3) line rate signals, or 6312 kbit/s (jt2) line signals specified in the japanese ntt technical reference for high speed digital leased circuits. an optional hdb3 codec is provided for the two itu-t line rates. txc-02302b, syn155c vlsi device (155-mbit/s synchronizer, clock and data out- put). provides complete sts-3/stm-1 frame synchronization on incoming 155 mbit/s signals in a single low-power unit. it has both clock and data outputs on the line side. txc-03001b, sot-1 vlsi device (sonet sts-1 overhead terminator). this device performs section, line and path overhead processing for sts-1 sonet signals. has programmable sts-1 or sts-n modes. txc-03003b, sot-3 vlsi device (stm-1/sts-3/sts-3c overhead terminator). this device performs section, line and path overhead processing for stm-1/sts-3/ sts-3c signals. compliant with ansi and itu-t standards. txc-03011, sot-1e vlsi device (sonet sts-1 overhead terminator). this device provides extended features relative to the 84-pin txc-03001b sot-1 devices, and it has a 144-pin package. txc-03109, e1fx8 vlsi device (8-channel e1 framer). an 8-channel framer for voice and data communications applications. this device handles all logical interfac- ing functionality to e1 lines and operates from a power supply of 3.3 volt. txc-03361, e123mux vlsi device (e1/e2/e3 mux/demux). the e123mux is a cmos vlsi device that provides the e13 functions needed to multiplex and demulti- plex 16 independent e1 signals to and from an e3 signal that conforms to the itu-t g.751 recommendation. the e123mux can also be configured to operate as an e12 or e23 multiplexer and demultiplexer. txc-04002b, adma-e1 vlsi device (dual e1 to tu-12 async mapper-desync). interconnects two e1 signals with any two asynchronous mode tu-12 tributaries car- ried in sdh au-3 rate payload interface. txc-04216, e1mx16 vlsi device (e1 mapper 16-channel). sixteen e1 2.048 mbit/s signals are mapped to and from asynchronous tributary unit-12s (tu-12s) or virtual tributary 2s (vt2s). txc-04252, qe1m vlsi device (quad e1 to au-4/vt2 or tu-12 async mapper- desync). interconnects four e1 signals with any four asynchronous mode vt2 or tu-12 tributaries carried in sdh au-4/au-3 rate payload interface. -183 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet txc-05101c, hdlc vlsi device (hdlc controller, 36-bit terminal i/o). high speed high level data link controller that sends and receives packets at line rates up to 51.84 mbit/s using either a nibble-parallel, byte-parallel, or serial interface. txc-05150, cdb vlsi device (cell delineation block). provides cell delineation for atm cells carried in a physical line at rates of 1.544 to 155 mbit/s. txc-06125, xbert vlsi device (bit error rate generator/receiver). programmable multi-rate test pattern generator and receiver in a single chip with serial, nibble-paral- lel, or byte-parallel interface capability. -184 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet standards documentation sources telecommunication technical standards and reference documentation may be obtained from the following organizations: ansi (u.s.a.): american national standards institute tel: 212-642-4900 11 west 42nd street fax: 212-302-1286 new york, new york 10036 web: www.ansi.org the atm forum (u.s.a., europe, asia): 2570 west el camino real tel: 650-949-6700 suite 304 fax: 650-949-6705 mountain view, ca 94040 web: www.atmforum.org atm forum europe office av. de tervueren 402 tel: 2 761 66 77 1150 brussels fax: 2 761 66 79 belgium web: www.euroinfo@atmforum.ocm atm forum asia-pacific office hamamatsucho suzuki building 3f tel: 3 3438 3694 1-2-11, hamamatsucho, minato-ku fax: 3 3438 3698 tokyo 105-0013, japan web: www.apinfo@atmforum.com bellcore (see telcordia) ccitt ( see itu-t) eia (u.s.a.): electronic industries association tel: 800-854-7179 (within u.s.a.) global engineering documents tel: 314-726-0444 (outside u.s.a.) 7730 carondelet avenue, suite 407 fax: 314-726-6418 clayton, mo 63105-3329 web: www.global.ihs.com etsi (europe): european telecommunications standards institute tel: 4 92 94 42 22 650 route des lucioles fax: 4 92 94 43 33 06921 sophia antipolis cedex web: www.etsi.org france go-mvip (u.s.a.): the global organization for multi-vendor integration protocol (go-mvip) tel: 800-669-6857 (within u.s.a.) tel: 903-769-3717 (outside u.s.a.) 3220 n street nw, suite 360 fax: 508-650-1375 washington, dc 20007 web: www.mvip.org -185 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet itu-t (international): publication services of international telecommunication union tel: 22 730 5111 fax: 22 733 7256 telecommunication standardization sector web: www.itu.int place des nations, ch 1211 geneve 20, switzerland mil-std (u.s.a.): dodssp standardization documents ordering desk tel: 215-697-2179 building 4 / section d fax: 215-697-1462 700 robbins avenue web: www.dodssp.daps.mil philadelphia, pa 19111-5094 pci sig (u.s.a.): pci special interest group tel: 800-433-5177 (within u.s.a.) 2575 ne kathryn street #17 tel: 503-693-6232 (outside u.s.a.) hillsboro, or 97124 fax: 503-693-8344 web: www.pcisig.com telcordia (u.s.a.): telcordia technologies, inc. tel: 800-521-core (within u.s.a.) attention - customer service tel: 908-699-5800 (outside u.s.a.) 8 corporate place fax: 908-336-2559 piscataway, nj 08854 web: www.telcordia.com ttc (japan): ttc standard publishing group of the telecommunications technology committee tel: 3 3432 1551 fax: 3 3432 1553 2nd floor, hamamatsucho - suzuki building, web: www.ttc.or.jp 1 2-11, hamamatsu-cho, minato-ku, tokyo -186 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet list of data sheet changes this change list identifies those areas within this updated qe1f- plus data sheet that have significant differ- ences relative to the previous and now superseded qe1f- plus data sheet: updated qe1f- plus data sheet: preliminary ed. 2, july 1999 previous qe1f- plus data sheet: product preview ed. 1, september 1998 the page numbers indicated below of this updated data sheet include changes relative to the previous data sheet. page number of updated data sheet s ummary of the change all changed edition number and date. changed product preview to preliminary. 1 added last line to system interfaces under features. changed "thin" to "low profile" in last line of features. changed product preview text to preliminary text in right margin . 2-4 updated table of contents and list of figures. 5 reduced two power dissipation values in first paragraph. changed "april 1992" to "nov. 1996 draft" in line prets 300 011. added one new line item under "ts0/crc-4 multiframe" and changed another. 7 changed third line item under second bullet to indicate that prbs testing is available only in 2 mbit/s transmission mode. 8 reduced power dissipation values on three lines in last two paragraphs. 21 changed "t1" to "e1" three times for receive fractional e1 gapped clock output in name/ function column. 22 for symbol prbsool, changed name/function column to indicate that pin is enabled only in 2 mbit/s transmission mode. 24 for symbol sysclk, modified name/function column to reduce permitted frequency range and inserted new table. 25 made extensive changes to both power requirements tables and deleted their notes. 27 changed test conditions for parameters v oh and v ol in last two tables. 28 changed test conditions for parameters v oh and v ol in second table. 30 changed test conditions for parameters v oh and v ol in last two tables. 31 changed test conditions for parameters v oh and v ol in last table. 32, 34 modified note 2 to change definition of minimum frequency of sysclk. 43-46, 52, 53 changed max for symbol t pw and added note 2. 48-51 changed max for symbols t pw , t pw(1) and t pw(2) , and added notes 2 and 3. 51, 52 increased min for symbols t su(1) and t su . 54, 56 changed "t1" to "e1" in figure titles and increased max for symbols t d(1) and t d in tables. 55 changed "t1" to "e1" and added "and 2 mbit/s mvip" in figure title. added descriptive information for 2 mbit/s mvip mode in diagram, table and note. 56, 57 added 2 mbit/s mvip mode information to figure 27. changed all min. values for transmission mode. 58 increased max for symbol t d . -187 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet 59 modified waveform diagram and table. deleted symbol t su(3) . changed symbol t h(3) to t h(2) . changed min value of t d(2) . changed parameter, min and typ for symbol t d(3) . changed 18 mhz to 19 mhz in note 2. added note 3. 60 changed waveform diagram and table. deleted symbol t su(3) . increased min for symbol t pw(1) . inserted new table rows for symbols t h(3) , t su(4) and t h(4) . changed min, typ and parameter for symbol t d(3) . changed parameters for some table rows to include references to note 4. 61 changed 18 mhz to 19 mhz in note 2. added notes 4, 5 and 6. 62 changed frequency value in note 2. 63 modified waveform diagram. inserted new parameters for symbols t su(5) and t h(4) in table. changed frequency value in note 2. added notes 4 and 5 for symbols t pw(1) and t h(4) . 63 added figure 34. 71 changed text in transmit highway section to agree with frame numbering change in figure 40. 72 changed frame numbering to "0 to 15" from "1 to 16" in figure 40. 73 changed text in receive highway section to agree with frame numbering change in figure 41. inserted "a regenerated" in fifth line of last paragraph. 74 changed frame numbering to "0 to 15" from "1 to 16" in figure 41. 86 inserted third line of first paragraph under fractional e1 capability to add 2 mbit/s mvip mode. modified columns that are headed config1 pin 43 and system interface in table. 88 added to seventh line of paragraph that begins with "the qe1f- plus ". added last two sentences to penultimate paragraph that begins with "for isdn applications". 91 added last sentence of fourth paragraph, "when control bit aags...". 96 made extensive changes to numeric values in throughput delay table. 109 added "and mvip" to third line and changed last sentence of first paragraph. clarified local loopback path description and figure 58 (to show ami codec capability). added last sentence of second paragraph. 110 clarified figure 59 to show ami codec capability. modified third sentence and added last sentence of first paragraph. 111 modified second and fifth sentences of first paragraph. 114 added reference to availability of bsdl file on transwitch web site. 118 modified second and third sentences of second paragraph to indicate action of software reset. added last paragraph. 123 changed slip buffer pointer status registers from read-only (r) status to read/write (rw). 128 changed description column for global software register to redefine its action. 131 added last sentence of note in first paragraph of description column. 132 modified third sentence of first paragraph. 135 changed first sentence of description for symbol prbsen to indicate prbs is enabled only in the 2 mbit/s transmission mode. 141 modified description column for symbols rxf and txf. 145, 146 inserted "high" and "or 2 mbit/s mvip mode" in description column for addresses 13a to 13f. 146 added last sentence to text paragraph. changed hdb3 to ami/hdb3 in description column for symbols rlp and llp. 147 changed description column for symbol insprbs to indicate that prbs test feature is limited to 2 mbit/s transmission mode. page number of updated data sheet s ummary of the change -188 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet 149 added last sentence to description column for symbol bpv. modified fourth sentence of first paragraph. 159 modified last sentence of description column for symbol ecrce. 160, 177 added last sentence to text paragraph. 178 added last sentence to description column for symbols erhis2-erhis0. 179 clarified description column for symbols rhis2-rhis0, 0101 condition in the table. 182-185 made extensive changes to update related products and standards documentation sources sections. 186-188 added list of data sheet changes section. 189 changed product preview paragraph to preliminary paragraph at lower right . page number of updated data sheet s ummary of the change -189 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet -notes- transwitch reserves the right to make changes to the product(s) or circuit(s) described herein without notice. no liability is assumed as a result of their use or application. transwitch assumes no liability for transwitch applications assistance, customer product design, soft- ware performance, or infringement of patents or services described herein. nor does transwitch warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of transwitch cov- ering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. preliminary information documents con- tain information on products in the sampling, pre-production or early production phases of the product life cycle. characteristic data and other specifications are subject to change. contact transwitch applications engineering for current information on this product. -190 - transwitch corporation 3 enterprise drive shelton, ct 06484 usa www.transwitch.com tel: 203-929-8810 fax: 203-926-9453 engines for global connectivity -191 - preliminary TXC-03114-mb ed. 2, july 1999 qe1f- plus TXC-03114 data sheet documentation update registration form if you would like to receive updated documentation for selected devices as it becomes available, please provide the information requested below (print clearly or type) then tear out this page, fold and mail it to the marketing communications department at transwitch. marketing communications will ensure that the relevant product information sheets, data sheets, application notes, technical bulletins and other publications are sent to you. you may also choose to provide the same information by fax (203.926.9453) , or by e-mail (info@txc.com) , or by telephone (203.929.8810) . most of these documents will also be made immediately available for direct download as adobe pdf files from the transwitch world wide web site ( www.transwitch.com ). name: ________________________________________________________________________________ company: ______________________________________ title: _________________________________ dept./mailstop: __________________________________________________________________________ street: ________________________________________________________________________________ city/state/zip: __________________________________________________________________________ if located outside u.s.a., please add - country: _________________ postal code:____________________ telephone: ________________________ ext.: _____________ fax: __________________________ e-mail: ________________________________________________ please provide the following details for the managers in charge of the following departments at your company location. department title name company/division __________________ __________________ engineering __________________ __________________ marketing __________________ __________________ please describe briefly your intended application(s) and indicate whether you would like to have a transwitch applications engineer contact you to provide further assistance: ____________________________________________________________________________________________ ____________________________________________________________________________________________ ____________________________________________________________________________________________ ____________________________________________________________________________________________ if you are also interested in receiving updated documentation for other transwitch device types, please list them below rather than submitting separate registration forms: ___________ ____________ ___________ ____________ ___________ ____________ ___________ ___________ ____________ ___________ ____________ ___________ ____________ ___________ please fold, tape and mail this page (see other side) or fax it to marketing communications at 203.926.9453. en g ines for global connectivity transwitch corporation attention: marketing communications dept. 3 enterprise drive shelton, ct 06484-4694 u.s.a. first class postage required please complete the registration form on this back cover sheet, and mail or fax it, if you wish to receive updated documentation on selected transwitch products as it becomes available. (fold back on this line first.) (fold back on this line second, then tape closed, stamp and mail.) transwitch corporation 3 enterprise drive shelton, ct 06484 usa www.transwitch.com tel: 203-929-8810 fax: 203-926-9453 3 enterprise drive shelton, ct 06484-4694 u.s.a. |
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